公开(公告)号：US3858238A

公开(公告)日：1974-12-31

申请号：US40092873

申请日：1973-09-26

Applicant: TOKYO SHIBAURA ELECTRIC CO

Inventor： NAKAMURA M ,  YONEZAWA T ,  AKATSUKA M ,  KATO T ,  WATANABE M

IPC: H01L21/225 ,  H01L29/04 ,  H01L29/167 ,  H01L3/14

CPC classification number: H01L21/2255 ,  H01L29/045 ,  H01L29/167 ,  Y10S148/04 ,  Y10S148/041 ,  Y10S148/097 ,  Y10S257/919

Abstract: A semiconductor device comprising a high impurity concentration region, the impurity consisting of arsenic and at least one impurity other than arsenic. The number of atoms of the arsenic is smaller than that of the other impurity.

Abstract translation: 一种半导体器件，包括高杂质浓度区域，由砷和砷以外的至少一种杂质构成的杂质。 砷的原子数小于其他杂质的原子数。

公开(公告)号：US3259815A

公开(公告)日：1966-07-05

申请号：US20605062

申请日：1962-06-28

Applicant: TEXAS INSTRUMENTS INC

Inventor： JOHNSON ROWLAND E ,  WURST JR ERNEST C

IPC: C30B11/00 ,  H01L21/00 ,  H01L29/00

CPC classification number: C30B29/42 ,  C30B11/00 ,  C30B29/40 ,  H01L21/00 ,  H01L29/00 ,  Y10S257/919

公开(公告)号：US08039874B2

公开(公告)日：2011-10-18

申请号：US11902391

申请日：2007-09-21

Applicant: Masatomo Eimitsu ,  Takanori Saeki

Inventor： Masatomo Eimitsu ,  Takanori Saeki

IPC: H01L27/118

CPC classification number: H01L27/11807 ,  H01L27/0207 ,  Y10S257/909 ,  Y10S257/919

Abstract: According to an aspect of the present invention, there is provided a semiconductor IC that includes a plurality of standard cells arranged in a first direction on a semiconductor substrate, and a first diffusion layer connected to a first power source and a second diffusion layer connected to a second power source in the each standard cell, wherein the first diffusion layers as well as the second diffusion layers of neighboring standard cells are integrally formed.

Abstract translation: 根据本发明的一个方面，提供了一种半导体IC，其包括在半导体衬底上沿第一方向布置的多个标准单元，以及连接到第一电源的第一扩散层和连接到 在每个标准单元中的第二电源，其中相邻标准单元的第一扩散层以及第二扩散层是一体形成的。

公开(公告)号：US06693332B2

公开(公告)日：2004-02-17

申请号：US10025047

申请日：2001-12-19

Applicant: Siva G. Narendra ,  Stephen H. Tang ,  Zachary Keer ,  Vivek K. De

Inventor： Siva G. Narendra ,  Stephen H. Tang ,  Zachary Keer ,  Vivek K. De

IPC: H01L2976

CPC classification number: G05F3/245 ,  Y10S257/919

Abstract: A current reference, which may be fabricated on a die, as part of an integrated circuit, or in various other forms, is disclosed. The current reference includes two current sources, both of which provide a substantially temperature stable output current, which may use a differencing circuit to provide a reference output current having a magnitude approximately equal to the difference between the magnitudes of the two substantially temperature stable output currents.

Abstract translation: 公开了可以在芯片上制造的作为集成电路的一部分或以各种其它形式的电流参考。 电流参考文献包括两个电流源，它们都提供基本上温度稳定的输出电流，其可以使用差分电路来提供参考输出电流，该参考输出电流的幅度近似等于两个基本上温度稳定的输出电流的幅度之差 。

公开(公告)号：US5892266A

公开(公告)日：1999-04-06

申请号：US865442

申请日：1997-05-30

Applicant: Yoshihiro Hirota ,  Toshiyuki Matsumoto ,  Guoliang Shou ,  Kazunori Motohashi

Inventor： Yoshihiro Hirota ,  Toshiyuki Matsumoto ,  Guoliang Shou ,  Kazunori Motohashi

IPC: H01L21/768 ,  H01L21/822 ,  H01L23/522 ,  H01L27/04 ,  H01L27/08 ,  H01L29/41

CPC classification number: H01L27/0805 ,  Y10S257/919

Abstract: The present invention reduces parasitic capacitance in a capacitive element distribution system by running unit electrode lead lines and common electrode lead lines in different directions so that the conductor lines may be sufficiently separated to suppress parasitic capacitance.

Abstract translation: 本发明通过在不同方向上运行单元电极引线和公共电极引线来减小电容元件分配系统中的寄生电容，使得导体线可以被充分地分离以抑制寄生电容。

公开(公告)号：US5818778A

公开(公告)日：1998-10-06

申请号：US824591

申请日：1997-03-26

Applicant: Sik K. Lui ,  Raymond M. Chu ,  David J. Pilling

Inventor： Sik K. Lui ,  Raymond M. Chu ,  David J. Pilling

IPC: G06F11/00 ,  G11C17/16 ,  G11C17/18 ,  G11C29/00

CPC classification number: G11C29/781 ,  G06F11/00 ,  G11C17/16 ,  G11C17/18 ,  G11C29/785 ,  Y10S257/919

Abstract: An antifuse redundancy circuit operates with transparency to external circuitry and users. In one embodiment, an antifuse redundancy circuit incorporates two antifuses rather than one. The circuit is arranged so that both antifuses may be simultaneously programmed and read. If a single antifuse is programmed without programming the other antifuse, the antifuse redundancy circuit will register a programmed antifuse. Additionally, if a single programmed antifuse is unintentionally deprogrammed after both antifuses in the redundancy circuit have been programmed, the antifuse redundancy circuit will continue to register a programmed antifuse. The result is both an increase in manufacturing yield and an increase in the reliability of integrated circuits utilizing antifuses.

Abstract translation: 反熔丝冗余电路对外部电路和用户具有透明度。 在一个实施例中，反熔丝冗余电路包括两个反熔丝而不是一个。 电路被布置成使得两个反熔丝可以被同时编程和读取。 如果在不编写其他反熔丝的情况下对单个反熔丝进行编程，则反熔丝冗余电路将注册编程的反熔丝。 此外，如果在冗余电路中的两个反熔丝编程之后，单个编程的反熔丝被无意地解除编程，则反熔丝冗余电路将继续注册编程的反熔丝。 结果是制造产量的增加和利用反熔丝的集成电路的可靠性的增加。

公开(公告)号：US5289040A

公开(公告)日：1994-02-22

申请号：US743697

申请日：1991-08-12

Applicant: Alan C. Rogers

Inventor： Alan C. Rogers

IPC: H01L23/525 ,  H01L27/088 ,  H01L23/48 ,  H01L27/02

CPC classification number: H01L23/525 ,  H01L27/088 ,  H01L2924/0002 ,  Y10S257/919

Abstract: An integrated circuit constructed using exposure and etching steps in an FET fabrication process incorporates electrical lead structures coupled to distributed IC components to compensate for process variation. The electrical lead structure (10,14,16,24,34is composed of an etchable conductive layer constructed in a configuration with graduated coupling widths (B,C,D,E . . . ) forming a graduated range of respective etchable dimensions arranged in an electrically coupled sequence. A primary lead (IA) is coupled at a first end to the widest coupling width (B). A plurality of secondary leads (0B,0C,0D,0E . . . ) distributed along the electrically coupled sequence of graduated coupling widths are coupled respectively to the distributed electrical component elements (P1B,P1C,P1D,P1E . . . ) (N1B,N1C,N1D,N1E . . . ) (RB,RC,RD,RE . . . ) of a distributed electrical component such as a PMOS transistor (P1) NMOS transistor (N1) or resistor (R). The graduated coupling widths (B,C,D,E . . . ) of the electrical lead structure (10,14,16,24,34) electrically couple the secondary leads (0B,0 C,0D,0E . . . ) to the primary lead (IA) through incremental portions of the electrically coupled sequence of graduated coupling widths. The electrical lead structure compensates for variation in exposure and etching steps by varying the number of distributed electrical component elements in the distributed circuit. In a distributed CMOS transistor structure (12) first and second source lead structures (14,16) are oriented to compensate for process variation in length (L) of etchable conductive layer gate segments (G) by varying the number of distributed complementary PMOS and NMOS transistor elements.

Abstract translation: 在FET制造工艺中使用曝光和蚀刻步骤构成的集成电路包括耦合到分布式IC组件的电引线结构以补偿工艺变化。 电引线结构（10,14,16,24,34）由可分级耦合宽度（B，C，D，E。）构造的可蚀刻导电层构成，其形成相应可蚀刻尺寸的刻度范围，其布置在 主引线（IA）在第一端耦合到最宽的耦合宽度（B）。多个次级引线（0B，0C，0D，0E ...）沿着电耦合序列 分级耦合宽度分别耦合到分布式电气元件（P1B，P1C，P1D，P1E ...）（N1B，N1C，N1D，N1E ...）（RB，RC，RD，RE ...） 诸如PMOS晶体管（P1）NMOS晶体管（N1）或电阻器（R）的分布式电气元件，电引线结构（10,14,16,16）的等级耦合宽度（B，C，D，E ...） 24,34）通过电耦合的研究生序列的增量部分将次级引线（0B，0C，0D，0E ...）电耦合到主引线（IA） d耦合宽度。 电引线结构通过改变分布式电路中的分布式电气元件的数量来补偿曝光和蚀刻步骤的变化。 在分布式CMOS晶体管结构（12）中，第一和第二源极引线结构（14,16）被定向以通过改变分布式互补PMOS的数量来补偿可蚀刻导电层栅极段（G）的长度（L）的工艺变化，以及 NMOS晶体管元件。

公开(公告)号：US4755479A

公开(公告)日：1988-07-05

申请号：US10667

申请日：1987-02-04

Applicant: Takao Miura

Inventor： Takao Miura

IPC: H01L21/266 ,  H01L21/3105 ,  H01L21/336 ,  H01L29/08 ,  H01L29/78 ,  H01L21/223 ,  H01L21/265

CPC classification number: H01L29/66598 ,  H01L21/266 ,  H01L21/3105 ,  H01L29/0847 ,  H01L29/6659 ,  H01L29/78 ,  Y10S148/044 ,  Y10S148/106 ,  Y10S148/157 ,  Y10S148/161 ,  Y10S257/90 ,  Y10S257/919 ,  Y10S438/965

Abstract: With an increase of integration density in an integrated circuit, the channel length of MIS FET becomes shorter and shorter, which causes a hot carrier effect. To solve the problem, the doping profile of source/drain regions and doping amount must be precisely controlled such that a strong electric field is not generated in a transition region from channel to drain. To obtain this objective, the present invention discloses a method, in which reflowed sidewalls of doped silicate glass having a gentle slope are formed on both sides of a gate electrode, and the gate electrode and the sidewalls thus formed are used as a mask for ion implantation. The depth of ion implantation and the doping amount change gradually from the channel region to the drain region avoiding a generation of the strong electric field and thus alleviates the short channel trouble. The present invention has also an effect of obtaining a passivation layer having gentle slope on the surface and avoiding a broken wire trouble of aluminum wiring.

Abstract translation: 随着集成电路集成密度的增加，MIS FET的沟道长度越来越短，从而导致热载流子效应。 为了解决这个问题，必须精确地控制源极/漏极区域的掺杂分布和掺杂量，使得在从通道到漏极的过渡区域中不产生强电场。 为了达到这个目的，本发明公开了一种方法，其中在栅电极的两侧形成具有平缓斜率的掺杂硅酸盐玻璃的回流侧壁，并且将这样形成的栅电极和侧壁用作离子掩模 植入。 离子注入的深度和掺杂量从沟道区逐渐变化到漏极区，避免了强电场的产生，从而缓解了短沟道故障。 本发明还具有获得在表面上具有缓和斜率的钝化层并避免铝布线断线的问题。

公开(公告)号：US4132573A

公开(公告)日：1979-01-02

申请号：US874592

申请日：1978-02-02

Applicant: Wolfgang Kraft

Inventor： Wolfgang Kraft

IPC: H01L21/22 ,  H01L21/74 ,  H01L21/761 ,  H01L21/20 ,  H01L21/225

CPC classification number: H01L21/2205 ,  H01L21/74 ,  H01L21/761 ,  Y10S257/919

Abstract: A monolithic integrated circuit is formed having semiconductor components disposed in surface regions of a semiconductor body, said regions being electrically isolated from the remaining semiconductor body by a pn-junction plane. The regions into which the semiconductor components are formed are electrically isolated by heavily doping surface areas of a substrate with phosphorus, antimony and/or arsenic impurities which are of the opposite conductivity from the substrate. After said doping, an epitaxial layer having a conductivity opposite to that of the substrate is formed over the entire substrate surface with a doping concentration lower than that of the substrate so that during subsequent high temperature processing steps, the substrate impurity out-diffuses into the epitaxial layer and the phosphorus of the heavily doped surface areas diffuses downwardly into the substrate to form a step-like pn-junction surface alternately extending into the substrate and into the epitaxial layer. During subsequent processing operations, an impurity of the same conductivity type as used in the substrate is diffused downwardly from the surface of the epitaxial layer to meet the out-diffused substrate impurity to complete the isolation of surface regions of the semiconductor body into which the semiconductor components are formed.

Abstract translation: 单片集成电路形成为具有设置在半导体主体的表面区域中的半导体部件，所述区域通过pn结平面与剩余的半导体本体电隔离。 形成半导体元件的区域通过用与衬底相反导电性的磷，锑和/或砷杂质重掺杂衬底的表面区域进行电隔离。 在所述掺杂之后，在整个衬底表面上形成具有与衬底相反的导电性的外延层，其掺杂浓度低于衬底的掺杂浓度，使得在随后的高温处理步骤期间，衬底杂质扩散到 外延层和重掺杂表面区域的磷向下扩散到衬底中以形成交替延伸到衬底中并进入外延层的阶梯状pn结表面。 在随后的处理操作期间，与衬底中使用的相同导电类型的杂质从外延层的表面向下扩散以满足外扩散的衬底杂质以完成半导体本体的表面区域的分离，半导体 组件形成。

公开(公告)号：US3863331A

公开(公告)日：1975-02-04

申请号：US28786372

申请日：1972-09-11

Applicant: RCA CORP

Inventor： SCHADE JR OTTO HEINRICH

IPC: H03F3/45 ,  H01L21/00 ,  H01L21/8234 ,  H01L27/02 ,  H01L27/088 ,  H01L29/78 ,  B01J17/00

CPC classification number: H01L27/0207 ,  H01L21/00 ,  Y10S257/919 ,  Y10S438/942

Abstract: Characteristics of photolithographically-defined planar semiconductor device pairs made from the same master are different, but many of the differences are regular in kind. To achieve a device pair in which the magnitude of the difference in the characteristics of the elements of the pair is reduced, two pairs are made from the same master. The first element of one pair is connected to the second element of the other pair so that the two operate as one composite element. The second element of the one pair is connected to the first element of the other, similarly for operation as another composite element the characteristics of which closely match those of the one composite element.

Abstract translation: 由相同的主机制造的光刻定义的平面半导体器件对的特性是不同的，但是许多差异是规范的。 为了实现一对装置对，其中该对的元件的特性的差异的大小减小，则由同一个主机制成两对。 一对中的第一个元件连接到另一对的第二个元件，使得它们作为一个复合元件进行操作。 一对的第二元件连接到另一个的第一元件，类似于作为另一个复合元件的操作，其特征与一个复合元件的特征紧密匹配。