公开(公告)号：US5753961A

公开(公告)日：1998-05-19

申请号：US467541

申请日：1995-06-07

Applicant: Masakatsu Tsuchiaki

Inventor： Masakatsu Tsuchiaki

IPC: H01L21/302 ,  H01L21/265 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8242 ,  H01L21/8244 ,  H01L27/108 ,  H01L27/11 ,  H01L27/118 ,  H01L29/00

CPC classification number: H01L27/10844 ,  H01L21/26586 ,  H01L21/3065 ,  H01L21/3086 ,  H01L21/76229 ,  H01L27/1087 ,  H01L27/10894 ,  H01L27/11 ,  H01L27/118 ,  Y10S148/05 ,  Y10S148/161

Abstract: A semiconductor device includes a body of semiconductor material having first trenches and second trenches. Each of the first trenches has vertical sidewalls and each of the second trenches has tapered sidewalls. First transistors are arranged in said semiconductor body and are isolated from each other by the first trenches. Second trenches are arranged in the semiconductor body and are isolated from each other by the second trenches.

Abstract translation: 半导体器件包括具有第一沟槽和第二沟槽的半导体材料体。 每个第一沟槽具有垂直侧壁，并且每个第二沟槽具有锥形侧壁。 第一晶体管布置在所述半导体本体中并且通过第一沟槽彼此隔离。 第二沟槽被布置在半导体本体中并且通过第二沟槽彼此隔离。

公开(公告)号：US5753558A

公开(公告)日：1998-05-19

申请号：US844384

申请日：1997-04-18

Applicant: Salman Akram ,  Charles Turner ,  Alan Laulusa

Inventor： Salman Akram ,  Charles Turner ,  Alan Laulusa

IPC: H01L21/02 ,  H01L21/311 ,  H01L21/768 ,  H01L21/20

CPC classification number: H01L28/84 ,  H01L21/31116 ,  H01L21/76804 ,  H01L28/82 ,  H01L28/90 ,  Y10S148/014 ,  Y10S148/161 ,  Y10S148/168 ,  Y10S438/978

Abstract: A method of forming a capacitor includes, a) providing a substrate; b) etching into the substrate to provide a depression in the substrate, the depression having a sidewall which is angled from vertical; c) providing a conformal layer of hemispherical grain polysilicon within the depression and over the angled sidewall, the layer of hemispherical grain polysilicon less than completely filling the depression; and d) ion implanting the hemispherical grain polysilicon layer with a conductivity enhancing impurity. Preferred methods of providing the depression where the substrate comprises SiO.sub.2 include a dry, plasma enhanced, anisotropic spacer etch utilizing reactant gases of CF.sub.4 and CHF.sub.3 provided to the substrate at a volumetric ratio of 1:1, and facet sputter etching.

公开(公告)号：US5658818A

公开(公告)日：1997-08-19

申请号：US516973

申请日：1995-08-18

Applicant: Salman Akram ,  Charles Turner ,  Alan Laulusa

Inventor： Salman Akram ,  Charles Turner ,  Alan Laulusa

IPC: H01L21/02 ,  H01L21/311 ,  H01L21/768 ,  H01L21/8242

CPC classification number: H01L28/84 ,  H01L21/31116 ,  H01L21/76804 ,  H01L28/82 ,  H01L28/90 ,  Y10S148/014 ,  Y10S148/161 ,  Y10S148/168 ,  Y10S438/978

Abstract: A method of forming a capacitor includes, a) providing a substrate; b) etching into the substrate to provide a depression in the substrate, the depression having a sidewall which is angled from vertical; c) providing a conformal layer of hemispherical grain polysilicon within the depression and over the angled sidewall, the layer of hemispherical grain polysilicon less than completely filling the depression; and d) ion implanting the hemispherical grain polysilicon layer with a conductivity enhancing impurity. Preferred methods of providing the depression where the substrate comprises SiO.sub.2 include a dry, plasma enhanced, anisotropic spacer etch utilizing reactant gases of CF.sub.4 and CHF.sub.3 provided to the substrate at a volumetric ratio of 1:1, and facet sputter etching.

Abstract translation: 一种形成电容器的方法包括：a）提供衬底; b）蚀刻到衬底中以在衬底中提供凹陷，凹陷具有与垂直成一定角度的侧壁; c）在凹陷内和在倾斜的侧壁上提供半球形晶粒多晶硅的保形层，半球形晶粒多晶硅层小于完全填充凹陷; 以及d）离子注入具有导电性增强杂质的半球状晶粒多晶硅层。 提供衬底包含SiO 2的凹陷的优选方法包括使用以1:1的体积比提供给衬底的CF 4和CHF 3的反应气体的干，等离子体增强的各向异性间隔物蚀刻和小面溅射蚀刻。

公开(公告)号：US5591675A

公开(公告)日：1997-01-07

申请号：US361835

申请日：1994-12-22

Applicant: Jae-woo Kim ,  Joon Kim ,  Jin-hong Kim

Inventor： Jae-woo Kim ,  Joon Kim ,  Jin-hong Kim

IPC: H01L21/28 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/44

CPC classification number: H01L21/76804 ,  Y10S148/161

Abstract: An interconnecting method for a semiconductor device is disclosed in which a conductive layer containing aluminum is formed on a lower structure formed on a substrate. An insulating layer is formed on the conductive layer. A photoresist pattern for defining a portion where an opening is to be made is formed on the insulating layer. Then, the insulating layer is isotropically etched by wet etching with the photoresist pattern as an etching mask. The insulating layer remaining after the isotropical etching is taper-etched by RIE to form the opening. To ensure that the conductive layer is exposed by the opening, the resultant structure is overetched by using a mixed gas of fluorocarbon-containing gas and oxygen. This resultant structure is RIE-sputtered using fluorocarbon-containing gas such that polymer or nonvolatile by-products generated when the opening such as a via hole is formed, are completely removed.

Abstract translation: 公开了一种用于半导体器件的互连方法，其中在形成在衬底上的下部结构上形成含有铝的导电层。 在导电层上形成绝缘层。 在绝缘层上形成用于限定要形成开口的部分的光刻胶图形。 然后，通过用蚀刻图案作为蚀刻掩模的湿蚀刻来各向同性蚀刻绝缘层。 在等温蚀刻之后残留的绝缘层通过RIE进行锥蚀刻以形成开口。 为了确保导电层被开口露出，通过使用含氟烃气体和氧气的混合气体对所得结构进行过蚀刻。 这种结构的结构是使用含氟烃气体进行RIE溅射，使得形成诸如通孔的开口产生的聚合物或非挥发性副产物被完全去除。

公开(公告)号：US5001080A

公开(公告)日：1991-03-19

申请号：US112305

申请日：1987-10-26

Applicant: Osamu Wada ,  Tatsuyuki Sanada ,  Shuichi Miura ,  Hideki Machida ,  Shigenobu Yamakoshi ,  Teruo Sakurai

Inventor： Osamu Wada ,  Tatsuyuki Sanada ,  Shuichi Miura ,  Hideki Machida ,  Shigenobu Yamakoshi ,  Teruo Sakurai

IPC: H01L21/263 ,  H01L21/308 ,  H01L21/8252 ,  H01L23/528 ,  H01L27/144 ,  H01L27/15 ,  H01S5/026

CPC classification number: H01L23/5283 ,  H01L21/2633 ,  H01L21/308 ,  H01L21/3081 ,  H01L21/3083 ,  H01L21/3086 ,  H01L21/8252 ,  H01L27/1443 ,  H01L27/15 ,  H01S5/0261 ,  H01L2924/0002 ,  Y10S148/051 ,  Y10S148/111 ,  Y10S148/161 ,  Y10S438/978

Abstract: A semiconductor device including a substrate having a low substrate surface formed in the substrate with a first gentle slope from the substrate surface; a single crystalline layer formed on the low substrate surface nearly level with the substrate surface and having a gentle slope facing the first gentle slope; an optical semiconductor element is constructed using the single crystalline layer. An electronic semiconductor element is constructed using the substrate surface. A wiring layer connects electrodes of the optical semiconductor element and the electronic semiconductor element through the first and the second gentle slopes.

公开(公告)号：US4997790A

公开(公告)日：1991-03-05

申请号：US566185

申请日：1990-08-13

Applicant: Michael P. Woo ,  Thomas C. Mele ,  Wayne J. Ray ,  Wayne M. Paulson

Inventor： Michael P. Woo ,  Thomas C. Mele ,  Wayne J. Ray ,  Wayne M. Paulson

IPC: H01L21/28 ,  H01L21/3205 ,  H01L21/60 ,  H01L21/768

CPC classification number: H01L21/76897 ,  H01L21/76885 ,  H01L24/11 ,  Y10S148/105 ,  Y10S148/161

Abstract: A self-aligned contact is formed in a multi-layer semiconductor device. In one form, conductive members are formed overlying a substrate material and a first insulating layer is deposited overlying the substrate material and the conductive members. A film of material is deposited on the first insulating layer and the film of material is patterned to form a sacrificial plug in an area where a contact is to be made. A second insulating layer is deposited on the device, and the device is made substantially planar. The second insulating layer is etched back to expose the sacrificial plug. The sacrificial plug is removed by selectively etching the device such that the first and second insulating layers are left substantially unaltered. An anisotropic etch of the device is performed to expose an area of the substrate material on which a contact is to be made, and to simultaneously form sidewall spacers along edges of the conductive members. A conductive layer is deposited onto the device and patterned, thereby forming a self-aligned contact.

Abstract translation: 在多层半导体器件中形成自对准接触。 在一种形式中，形成覆盖衬底材料的导电构件，并且沉积覆盖衬底材料和导电构件的第一绝缘层。 将材料膜沉积在第一绝缘层上，并且将材料膜图案化以在要进行接触的区域中形成牺牲插塞。 第二绝缘层沉积在器件上，并且器件基本上是平面的。 将第二绝缘层回蚀刻以暴露牺牲插头。 通过选择性地蚀刻该器件以使得第一绝缘层和第二绝缘层基本上保持不变而去除牺牲插塞。 执行器件的各向异性蚀刻以暴露要在其上形成触点的衬底材料的区域，并且同时沿着导电构件的边缘形成侧壁间隔物。 导电层沉积在器件上并图案化，从而形成自对准接触。

公开(公告)号：US4925809A

公开(公告)日：1990-05-15

申请号：US214501

申请日：1988-07-01

Applicant: Tetsujiro Yoshiharu ,  Haruo Kamise

Inventor： Tetsujiro Yoshiharu ,  Haruo Kamise

IPC: H01L21/20 ,  H01L21/22 ,  H01L21/311 ,  H01L21/314

CPC classification number: H01L21/3144 ,  H01L21/2205 ,  H01L21/31111 ,  Y10S148/161 ,  Y10S438/916 ,  Y10S438/959

Abstract: A semiconductor wafer on which silicon or the like is epitaxially grown and p-type or n-type impurities are doped and which has at the rear surface except for the peripheral edge portion thereof a blocking film for preventing jumping out of impurities therefrom which causes auto-doping, thereby preventing silicon particles from being produced at the peripheral surface and preventing the semiconductor wafer from being contaminated by the silicon particles during the manufacturing of a semiconductor device.

Abstract translation: 在其上外延生长硅等的半导体晶片，掺杂p型或n型杂质，除了其外围边缘部分之外还具有用于防止从其中排出杂质的阻挡膜的后表面，其导致自动 从而防止在半导体器件的制造期间在外围表面产生硅颗粒并防止半导体晶片被硅颗粒污染。

公开(公告)号：US06476447B1

公开(公告)日：2002-11-05

申请号：US09660385

申请日：2000-09-12

Applicant: Shunpei Yamazaki ,  Akira Mase ,  Masaaki Hiroki ,  Yasuhiko Takemura ,  Hongyong Zhang ,  Hideki Uochi

Inventor： Shunpei Yamazaki ,  Akira Mase ,  Masaaki Hiroki ,  Yasuhiko Takemura ,  Hongyong Zhang ,  Hideki Uochi

IPC: H01L2701

CPC classification number: H01L27/124 ,  G02F2001/136245 ,  G09G2300/0823 ,  H01L27/1214 ,  H01L29/4908 ,  H01L29/66757 ,  H01L29/78618 ,  Y10S148/161 ,  Y10S148/163

Abstract: A transistor adapted to be used in an active-matrix liquid-crystal display, the channel length, of the distance between the source region and the drain region, is made larger than the length of the gate electrode taken in the longitudinal direction of the channel. Offset regions are formed in the channel region on the sides of the source and drain regions. No or very weak electric fields is applied to these offset regions from the gate electrode.

Abstract translation: 适于在有源矩阵液晶显示器中使用的晶体管使得源极区域和漏极区域之间的距离的沟道长度大于在沟道的纵向方向上获取的栅电极的长度 。 偏移区域形成在源极和漏极区域的侧面上的沟道区域中。 没有或非常弱的电场施加到来自栅电极的这些偏移区域。

公开(公告)号：US6147375A

公开(公告)日：2000-11-14

申请号：US151269

申请日：1998-09-11

Applicant: Shunpei Yamazaki ,  Akira Mase ,  Masaaki Hiroki ,  Yasuhiko Takemura ,  Hongyong Zhang ,  Hideki Uochi

Inventor： Shunpei Yamazaki ,  Akira Mase ,  Masaaki Hiroki ,  Yasuhiko Takemura ,  Hongyong Zhang ,  Hideki Uochi

IPC: G02F1/1362 ,  H01L21/336 ,  H01L21/77 ,  H01L21/84 ,  H01L27/12 ,  H01L29/49 ,  H01L29/786 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC classification number: H01L29/66757 ,  H01L27/1214 ,  H01L29/4908 ,  H01L29/78618 ,  G02F2001/136245 ,  G09G2300/0823 ,  Y10S148/161 ,  Y10S148/163

Abstract: A wiring formed on a substrate is oxidized and the oxide is used as a mask for forming source and drain impurity regions of a transistor, or as a material for insulating wirings from each other, or as a dielectric of a capacitor. The thickness of the oxide is determined depending on the purpose of the oxide. In a transistor adapted to be used in an active-matrix liquid-crystal display, the channel length, the distance between the source region and the drain region, is made larger than the length of the gate electrode taken in the longitudinal direction of the channel. Offset regions are formed in the channel region on the sides of the source and drain regions. No or very weak electric fields are applied to these offset regions from the gate electrode.

Abstract translation: 形成在基板上的布线被氧化，并且氧化物用作用于形成晶体管的源极和漏极杂质区域或用作彼此绝缘布线的材料的掩模，或者用作电容器的电介质。 氧化物的厚度取决于氧化物的目的。 在适用于有源矩阵液晶显示器的晶体管中，沟道长度，源极区域和漏极区域之间的距离大于在沟道的纵向方向上取得的栅电极的长度 。 偏移区域形成在源极和漏极区域的侧面上的沟道区域中。 没有或非常弱的电场施加到来自栅电极的这些偏移区域。

公开(公告)号：US5849611A

公开(公告)日：1998-12-15

申请号：US455156

申请日：1995-05-31

Applicant: Shunpei Yamazaki ,  Akira Mase ,  Masaaki Hiroki ,  Yasuhiko Takemura ,  Hongyong Zhang ,  Hideki Uochi

Inventor： Shunpei Yamazaki ,  Akira Mase ,  Masaaki Hiroki ,  Yasuhiko Takemura ,  Hongyong Zhang ,  Hideki Uochi

IPC: G02F1/1362 ,  H01L21/336 ,  H01L21/77 ,  H01L21/84 ,  H01L27/12 ,  H01L29/49 ,  H01L29/786 ,  H01L21/32

CPC classification number: H01L29/66757 ,  H01L27/1214 ,  H01L29/4908 ,  H01L29/78618 ,  G02F2001/136245 ,  G09G2300/0823 ,  Y10S148/161 ,  Y10S148/163

Abstract: A wiring formed on a substrate is oxidized and the oxide is used as a mask for forming source and drain impurity regions of a transistor, or as a material for insulating wirings from each other, or as a dielectric of a capacitor. Thickness of the oxide is determined depending on purpose of the oxide. In a transistor adapted to be used in an active-matrix liquid-crystal display, the channel length, or the distance between the source region and the drain region, is made larger than the length of the gate electrode taken in the longitudinal direction of the channel. Offset regions are formed in the channel region on the sides of the source and drain regions. No or very weak electric field is applied to these offset regions from the gate electrode.

Abstract translation: 形成在基板上的布线被氧化，并且氧化物用作用于形成晶体管的源极和漏极杂质区域或用作彼此绝缘布线的材料的掩模，或者用作电容器的电介质。 氧化物的厚度根据氧化物的目的而确定。 在适于用于有源矩阵液晶显示器的晶体管中，沟道长度或源极区域和漏极区域之间的距离大于沿着栅极电极的纵向取向的栅电极的长度 渠道。 偏移区域形成在源极和漏极区域的侧面上的沟道区域中。 没有或非常弱的电场被施加到来自栅电极的这些偏移区域。