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    Multiplication circuit
    3.
    发明授权
    Multiplication circuit 失效
    乘法电路

    公开(公告)号：US5835387A

    公开(公告)日：1998-11-10

    申请号：US791022

    申请日：1997-01-27

    Applicant: Gouliang Shou ,  Kazunori Motohashi ,  Sunao Takatori ,  Makoto Yamamoto

    Inventor： Gouliang Shou ,  Kazunori Motohashi ,  Sunao Takatori ,  Makoto Yamamoto

    IPC: G06J1/00

    CPC classification number: G06J1/00

    Abstract: Multiplication is performed including accumulation at high speed by a small quantity of hardware. Analog voltage X.sub.i corresponding to each element of the first input data string is input to capacitance switching circuits 10.sub.1 to 10.sub.n through input terminals 1.sub.1 to 1.sub.n. m bit of digital control data A.sub.i corresponding to each element of the second input data string are input to each capacitance switching circuit 10.sub.i, and each bit a.sub.j of the control signal A.sub.j is input to the corresponding multiplexer circuit 6.sub.ij. In the multiplexer circuit 6.sub.ij, the capacitances C.sub.ij corresponding to the value of each bit of the control signal a.sub.j are connected to the input terminal 1.sub.i or the reference charge V.sub.STD. The voltages corresponding to the products of inputted analog voltages X.sub.1 and the control signals A.sub.i are outputted from each capacitance switching circuit 10.sub.j. The output voltages of each capacitance switching circuit 10.sub.i are parallelly inputted to the operational amplifier 3 connected by a feedback capacitance Cf, and the sum of the input voltages is outputted from the operational amplifier 3. On the other hand, in order to provide a multiplication circuit of high calculation speed without deteriorating the calculation accuracy and circuit density, a multiplication circuit according to the present invention has a MOS switch or MOS multiplexer the MOS of which has a gate with width and length so that a time constant defined by the input capacitance and the switch etc. is constant.

    Abstract translation: 执行乘法，包括由少量硬件高速累积。 对应于第一输入数据串的每个元件的模拟电压Xi通过输入端子11至1n输入到电容切换电路101至10n。 对应于第二输入数据串的每个元件的数字控制数据Ai的m位被输入到每个电容切换电路10i，并且控制信号Aj的每个位aj被输入到相应的多路复用器电路6ij。 在复用器电路6ij中，与控制信号aj的每个位的值相对应的电容Cij连接到输入端1i或参考电荷VSTD。 从各电容切换电路10j输出与输入的模拟电压X1的乘积对应的电压和控制信号Ai。 每个电容切换电路10i的输出电压被并行地输入到由反馈电容Cf连接的运算放大器3，并且从运算放大器3输出输入电压的和。另一方面，为了提供乘法 具有高计算速度的电路，而不降低计算精度和电路密度，根据本发明的乘法电路具有MOS开关或MOS多路复用器，其MOS具有宽度和长度的栅极，使得由输入电容定义的时间常数 并且开关等是恒定的。

    Interface circuit having a plurality of thresholding circuits
    4.
    发明授权
    Interface circuit having a plurality of thresholding circuits 失效
    接口电路具有多个阈值电路

    公开(公告)号：US5661482A

    公开(公告)日：1997-08-26

    申请号：US536243

    申请日：1995-09-29

    Applicant: Guoliang Shou ,  Kazunori Motohashi ,  Makoto Yamamoto ,  Sunao Takatori

    Inventor： Guoliang Shou ,  Kazunori Motohashi ,  Makoto Yamamoto ,  Sunao Takatori

    IPC: H03M1/34 ,  G06J1/00 ,  H03M1/74 ,  H03K19/0175 ,  H03K19/00

    CPC classification number: G06J1/00

    Abstract: An interface circuit comprising a digital to analog converter which comprises a register for receiving and holding each bit of a digital signal, a capacitive coupling for integrating total bits held in the register with weighting, an inverted amplifier circuit for receiving an output of the capacitive coupling and for outputting an analog output voltage, and a feedback capacitance for connecting an outputs of the inverted amplifier circuit to an input of the inverted amplifier circuit, an analog signal line to which the analog output voltage is connected, and an analog to digital converter which comprises a plurality thresholding circuits with stepwise thresholds to which the analog signal line is commonly inputted, each the thresholding circuit receiving outputs of the thresholding circuits of higher threshold with weighting so that the thresholding circuits repeatedly change the outputs from high level to low level or from low level to high level.

    Abstract translation: 一种接口电路，包括数模转换器，其包括用于接收和保持数字信号的每一位的寄存器，用于将保持在寄存器中的总比特积分为加权的电容耦合，反相放大器电路，用于接收电容耦合的输出 并且用于输出模拟输出电压，以及用于将反相放大器电路的输出连接到反相放大器电路的输入的反馈电容，连接有模拟输出电压的模拟信号线以及模数转换器， 包括具有逐步阈值的多个阈值电路，模拟信号线被共同地输入到该阈值电路中，每个阈值电路通过加权接收具有较高阈值的阈值电路的输出，使得阈值电路将输出从高电平重复地改变为低电平或从 低级到高级。

    Sampling and holding circuit
    5.
    发明授权
    Sampling and holding circuit 失效
    取样保持电路

    公开(公告)号：US5606274A

    公开(公告)日：1997-02-25

    申请号：US512317

    申请日：1995-08-08

    Applicant: Guoliang Shou ,  Kazunori Motohashi ,  Makoto Yamamoto ,  Sunao Takatori

    Inventor： Guoliang Shou ,  Kazunori Motohashi ,  Makoto Yamamoto ,  Sunao Takatori

    IPC: G11C27/02

    CPC classification number: G11C27/026 ,  G11C27/024

    Abstract: An analog input voltage is inputted to a first sample and hold circuit and a second sample and hold circuit is connected to an output of the first sample and hold circuit. The output of the first and second sample and hold circuits are inputted to a multiplexer which alternatively outputs the output of first sample and hold circuit or the second sample and hold circuit. When one of the first and second sample and hold circuits is refreshed, the output of the other sample and hold circuit is selected to be outputted from the multiplexer.

    Abstract translation: 模拟输入电压被输入到第一采样保持电路，第二采样和保持电路连接到第一采样和保持电路的输出。 第一和第二采样和保持电路的输出被输入到多路复用器，该多路复用器交替地输出第一采样保持电路或第二采样和保持电路的输出。 当第一和第二取样和保持电路中的一个被刷新时，另一采样和保持电路的输出被选择为从多路复用器输出。

    Vector absolute--value calculation circuit
    6.
    发明授权
    Vector absolute--value calculation circuit 失效
    矢量绝对值计算电路

    公开(公告)号：US5958002A

    公开(公告)日：1999-09-28

    申请号：US905784

    申请日：1997-08-12

    Applicant: Changming Zhou ,  Guoliang Shou ,  Kunihiko Suzuki ,  Kazunori Motohashi ,  Makoto Yamamoto ,  Sunao Takatori

    Inventor： Changming Zhou ,  Guoliang Shou ,  Kunihiko Suzuki ,  Kazunori Motohashi ,  Makoto Yamamoto ,  Sunao Takatori

    IPC: G06G7/25 ,  G06G7/22 ,  G06G7/00 ,  G06G7/16

    CPC classification number: G06G7/22

    Abstract: A highly accurate vector absolute-value calculation circuit uses analog processing and minimal hardware. Signal voltages corresponding to an I component (real number part) and a Q component (imaginary number part) are input to a first absolute-value calculation circuit 13 and a second absolute-value calculation circuit 14 through terminals 11 and 12, respectively, and they are each converted into absolute-value signals. The component I absolute-value and component Q absolute-value are compared in a comparison circuit 20. According to the result, the larger absolute-value signals are output to an input capacitor 23 of a neural computation circuit, and the smaller absolute-value signals are output to an input capacitor 24 by controlling multiplexers 21 and 22. The capacity ratio of a feedback capacitor 26 of a neural computation circuit and input capacitors 23 and 24 is 11:10:5. The complex number absolute-value calculated by the following formula is output from an output terminal 27. ##EQU1##

    Abstract translation: 高精度矢量绝对值计算电路采用模拟处理和最小硬件。 对应于I分量（实数部分）和Q分量（虚数部分）的信号电压分别通过端子11和12输入到第一绝对值计算电路13和第二绝对值计算电路14，以及 它们都被转换为绝对值信号。 在比较电路20中比较分量I绝对值和分量Q绝对值。根据结果，较大的绝对值信号被输出到神经计算电路的输入电容器23，并且较小的绝对值 通过控制多路复用器21和22将信号输出到输入电容器24.神经计算电路和输入电容器23和24的反馈电容器26的容量比为11:10:5。 从输出端子27输出由下式计算的复数绝对值。

    Multiplication and addition circuit
    7.
    发明授权
    Multiplication and addition circuit 失效
    乘法和加法电路

    公开(公告)号：US5907496A

    公开(公告)日：1999-05-25

    申请号：US921578

    申请日：1997-09-02

    Applicant: Guoliano Shou ,  Kazunori Motohashi

    Inventor： Guoliano Shou ,  Kazunori Motohashi

    IPC: G06J1/00 ,  G06G7/16

    CPC classification number: G06J1/00

    Abstract: A multiplication and addition circuit multiplies each of a plurality of analog voltages by a corresponding digital multiplier and then adds up the products. First, each bit corresponding to each of the multipliers is multiplied with the corresponding analog voltage. Then, the products for each bit of the multiplier are added. The results are weighted by each bit weight and the weighted values are added. The multipliers are rotated so that there is the number of data transmission errors is lowered.

    Abstract translation: 乘法和加法电路通过相应的数字乘法器将多个模拟电压中的每一个相乘，然后将乘积相加。 首先，对应于每个乘法器的每个位乘以对应的模拟电压。 然后，添加乘数的每一位的乘积。 结果通过每个位权重进行加权，并加入加权值。 旋转乘法器使得数据传输错误的数量降低。

    Weight addition circuit
    8.
    发明授权
    Weight addition circuit 失效
    加权电路

    公开(公告)号：US5815021A

    公开(公告)日：1998-09-29

    申请号：US686761

    申请日：1996-07-26

    Applicant: Guoliang Shou ,  Changming Zhou ,  Kazunori Motohashi ,  Makoto Yamamoto ,  Sunao Takatori

    Inventor： Guoliang Shou ,  Changming Zhou ,  Kazunori Motohashi ,  Makoto Yamamoto ,  Sunao Takatori

    IPC: G06G7/14 ,  G06J1/00 ,  G06G7/16

    CPC classification number: G06J1/00 ,  G06G7/14

    Abstract: The present invention provides a weighted addition circuit for sampling, holding and performing weighted addition by a circuit smaller than a conventional one. In the weighted addition circuit of to the present invention, a capacitive coupling is connected to a plurality of switches which are further connected only to an input voltage. A voltage is held and a weight is added in the capacitive coupling.

    Abstract translation: 本发明提供一种加权加法电路，用于通过比传统电路小的电路进行采样，保持和执行加权相加。 在本发明的加权加法电路中，电容耦合连接到多个开关，该开关进一步仅与输入电压相连。 在电容耦合中保持电压并加上重量。

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