公开(公告)号：US20240172415A1

公开(公告)日：2024-05-23

申请号：US18092089

申请日：2022-12-30

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Hongbin ZHU ,  Weihua CHENG ,  Wei LIU ,  Wenyu HUA ,  Bingjie YAN ,  Zichen LIU

IPC: H10B12/00 ,  H10B53/30 ,  H10B63/00 ,  H10B63/10

CPC classification number: H10B12/315 ,  H10B12/05 ,  H10B53/30 ,  H10B63/10 ,  H10B63/34

Abstract: In certain aspects, a semiconductor device includes a vertical transistor, a metal bit line, and a pad layer. The vertical transistor includes a semiconductor body extending in a first direction, and a gate structure coupled to at least one side of the semiconductor body. The gate structure includes a gate dielectric and a gate electrode. The metal bit line extends in a second direction perpendicular to the first direction and coupled to a terminal of the vertical transistor via an ohmic contact. The pad layer is positioned between the gate electrode and the metal bit line in the first direction. The gate dielectric and the pad layer have different dielectric materials.

公开(公告)号：US11963372B2

公开(公告)日：2024-04-16

申请号：US17469372

申请日：2021-09-08

Applicant: SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION

Inventor： Yun Seog Lee ,  Hyunjoon Lee

IPC: H10B63/00 ,  G06N3/063 ,  H10N70/20

CPC classification number: H10B63/845 ,  G06N3/063 ,  H10B63/34 ,  H10N70/24

Abstract: Disclosed is a three-terminal electro-chemical memory cell with a vertical structure for neuromorphic computation, including a circumferential hole, first and second conductive electrode layers sequentially stacked along an outer surface of the circumferential hole, an electrolyte layer formed along an inner surface of the circumferential hole and connected to one end of each of the first and second conductive electrode layers, and a gate electrode disposed parallel to the electrolyte layer in an inner surface direction of the circumferential hole.

公开(公告)号：US20240114810A1

公开(公告)日：2024-04-04

申请号：US18303682

申请日：2023-04-20

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Fu-Ting Sung ,  Jhih-Bin Chen ,  Hung-Shu Huang ,  Hong Ming Liu ,  Hsia-Wei Chen ,  Yu-Wen Liao ,  Wen-Ting Chu

IPC: H10N70/00 ,  H01L23/522 ,  H01L23/528 ,  H10B63/00 ,  H10N70/20

CPC classification number: H10N70/841 ,  H01L23/5226 ,  H01L23/5283 ,  H10B63/34 ,  H10N70/063 ,  H10N70/253 ,  H10N70/826

Abstract: A semiconductor structure includes: an etch-stop dielectric layer overlying a substrate and including a first opening therethrough; a silicon oxide plate overlying the etch-stop dielectric layer and including a second opening therethrough; a first conductive structure including a first electrode and extending through the second opening and the first opening; a memory film contacting a top surface of the first conductive structure and including a material that provides at least two resistive states having different electrical resistivity; and a second conductive structure including a second electrode and contacting a top surface of the memory film.

公开(公告)号：US11942147B2

公开(公告)日：2024-03-26

申请号：US17872111

申请日：2022-07-25

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Marcus Johannes Henricus Van Dal ,  Gerben Doornbos ,  Georgios Vellianitis ,  Blandine Duriez ,  Mauricio Manfrini

IPC: G11C11/00 ,  G11C13/00 ,  H10B63/00 ,  H10N70/00 ,  H10N70/20

CPC classification number: G11C13/0007 ,  G11C13/0069 ,  H10B63/34 ,  H10B63/80 ,  H10N70/011 ,  H10N70/253 ,  H10N70/841 ,  H10N70/8833

Abstract: A memory device is provided, which may include a first electrode, a memory layer stack including at least one semiconducting metal oxide layer and at least one hydrogen-containing metal layer, and a second electrode. A semiconductor device is provided, which may include a semiconducting metal oxide layer containing a source region, a drain region, and a channel region, a hydrogen-containing metal layer located on a surface of the channel region, and a gate electrode located on the hydrogen-containing metal layer. Each hydrogen-containing metal layer may include at least one metal selected from platinum, iridium, osmium, and ruthenium at an atomic percentage that is at least 90%, and may include hydrogen atoms at an atomic percentage in a range from 0.001% to 10%. Hydrogen atoms may be reversibly impregnated into a respective semiconducting metal oxide layer to change resistivity and to encode a memory bit.

公开(公告)号：US20240099026A1

公开(公告)日：2024-03-21

申请号：US18519964

申请日：2023-11-27

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Haitao Liu ,  Durai Vishak Nirmal Ramaswamy

IPC: H10B63/00 ,  G11C5/12 ,  G11C13/00 ,  H01L21/8234 ,  H01L27/12 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786 ,  H10N70/00 ,  H10N70/20

CPC classification number: H10B63/84 ,  G11C5/12 ,  G11C13/0002 ,  H01L21/823487 ,  H01L27/1225 ,  H01L29/4908 ,  H01L29/66666 ,  H01L29/66795 ,  H01L29/7827 ,  H01L29/78642 ,  H01L29/7869 ,  H01L29/78696 ,  H10B63/22 ,  H10B63/24 ,  H10B63/34 ,  H10N70/011 ,  H10N70/245 ,  H10N70/828 ,  H10N70/841 ,  H10N70/883 ,  G11C11/401 ,  G11C2213/79

Abstract: Semiconductor devices are disclosed. A semiconductor device may include a hybrid transistor configured in a vertical orientation. The hybrid transistor may include a gate electrode, a drain material, a source material, and a channel material operatively coupled between the drain material and the source material. The source material and the drain material include a first material and the channel material includes a second, different material.

公开(公告)号：US20240074211A1

公开(公告)日：2024-02-29

申请号：US18238291

申请日：2023-08-25

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Chandra Mouli ,  Haitao Liu ,  Durai Vishak Nirmal Ramaswamy

IPC: H10B63/00 ,  G11C5/06 ,  H10B63/10 ,  H10N70/00

CPC classification number: H10B63/34 ,  G11C5/063 ,  H10B63/10 ,  H10B63/845 ,  H10N70/883

Abstract: Some embodiments include apparatuses and methods of operating the apparatuses. One of the apparatuses includes a conductive region; a memory cell including a memory element, a first portion, a second portion, a dielectric portion, and a third portion; and a data line formed over the second and third portions of the memory cell. The memory element is formed over the conductive region. The first portion is formed over the memory element and includes a first conductive material. The second portion is formed over the first portion and includes a second conductive material. The dielectric portion includes a first side adjacent the memory element, the first portion, and the second portion. The third portion includes a third conductive material and is adjacent a second side of the dielectric portion and separated from the memory element, the first portion, and the second portion by the dielectric portion.

公开(公告)号：US11903221B2

公开(公告)日：2024-02-13

申请号：US17156320

申请日：2021-01-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chenchen Wang ,  Chun-Chieh Lu ,  Chi On Chui ,  Yu-Ming Lin ,  Sai-Hooi Yeong

IPC: H10B63/00 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786 ,  H10B61/00

CPC classification number: H10B63/84 ,  H01L29/42392 ,  H01L29/66666 ,  H01L29/78642 ,  H10B61/22 ,  H10B63/34

Abstract: A device includes a first transistor over a substrate, a second transistor disposed over the first transistor, and a memory element disposed over the second transistor. The second transistor includes a channel layer, a gate dielectric layer surrounding a sidewall of the channel layer, and a gate electrode surrounding a sidewall of the gate dielectric layer.

公开(公告)号：US20240049479A1

公开(公告)日：2024-02-08

申请号：US18177064

申请日：2023-03-01

Applicant: Kioxia Corporation

Inventor： Yuki ITO ,  Daisaburo TAKASHIMA ,  Hidehiro SHIGA ,  Yoshiki KAMATA

IPC: H10B63/00 ,  H10B61/00

CPC classification number: H10B63/845 ,  H10B63/34 ,  H10B61/22

Abstract: A variable resistance non-volatile memory includes a memory cell including a core portion extending in a first direction above a semiconductor substrate, a variable resistance layer extending in a first direction and in contact with the core portion, a semiconductor layer extending in a first direction and in contact with the variable resistance layer, an insulator layer extending in a first direction and in contact with the semiconductor layer, and a first voltage application electrode extending in a second direction crossing the first direction and in contact with the insulator layer. An impurity concentration of the semiconductor layer is non-uniform, such that an impurity concentration of a first portion of the semiconductor layer in contact with the insulator layer is at least ten times higher than an impurity concentration of a second portion of the semiconductor layer in contact with the variable resistance layer.

公开(公告)号：US20240049465A1

公开(公告)日：2024-02-08

申请号：US18101530

申请日：2023-01-25

Applicant: SK hynix Inc.

Inventor： In Ku KANG

IPC: H10B43/27 ,  H10B41/27 ,  H10B63/00

CPC classification number: H10B43/27 ,  H10B41/27 ,  H10B63/34

Abstract: Provided herein are a semiconductor memory device and a method of manufacturing the semiconductor memory device. The semiconductor memory device includes a gate stacked body including a plurality of interlayer insulating layers and a plurality of conductive layers that are alternately stacked, wherein a top-most conductive layer, among the plurality of conductive layers, corresponds to a backgate line and the rest of the plurality of conductive layers correspond to word lines, and a vertical channel structure passing through the gate stacked body. A first part of the vertical channel structure passing through the plurality of interlayer insulating layers and the plurality of conductive layers corresponding to the word lines has a circular structure in a plan view, and a second part of the vertical channel structure passing through the conductive layer corresponding to the backgate line has a pair of semicircular structures that are separated from each other in a plan view.

公开(公告)号：US11876046B2

公开(公告)日：2024-01-16

申请号：US16869096

申请日：2020-05-07

Applicant: SK hynix Inc.

Inventor： Ki Hong Lee

IPC: H01L23/528 ,  H01L23/532 ,  H01L23/535 ,  H01L29/06 ,  H01L21/768 ,  H01L21/762 ,  H01L21/311 ,  H10B41/10 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40 ,  H10B63/00 ,  H10N70/20 ,  H10N70/00 ,  H10B41/27 ,  H10B43/27

CPC classification number: H01L23/528 ,  H01L21/31116 ,  H01L21/762 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/535 ,  H01L23/53295 ,  H01L29/0649 ,  H10B41/10 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40 ,  H10B63/30 ,  H10B63/845 ,  H10N70/231 ,  H10N70/25 ,  H10N70/823 ,  H10B41/27 ,  H10B43/27 ,  H10B63/34

Abstract: A semiconductor device includes a wiring structure, a stacked structure located over the wiring structure, channel structures passing through the stacked structure, contact plugs passing through the stacked structure and electrically connected to the wiring structure, and insulating spacers each including loop patterns surrounding a sidewall of each of the contact plugs and stacked along the sidewall of each of the contact plugs.