公开(公告)号：US10084032B2

公开(公告)日：2018-09-25

申请号：US15582963

申请日：2017-05-01

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Wei-Li Huang ,  Chi-Cheng Chen ,  Hon-Lin Huang ,  Chien-Chih Chou ,  Chin-Yu Ku ,  Chen-Shien Chen

IPC: H01L21/311 ,  H01L21/3213 ,  H01L49/02 ,  H01F41/04 ,  H01F27/28 ,  H01L27/22 ,  H01L23/522 ,  H01L23/64

CPC classification number: H01L28/10 ,  H01F27/2804 ,  H01F41/041 ,  H01L21/32134 ,  H01L21/32138 ,  H01L21/32139 ,  H01L23/5227 ,  H01L23/645 ,  H01L27/222 ,  H01L2924/1206

Abstract: A method of manufacturing a semiconductor device and the semiconductor device are provided in which a plurality of layers with cobalt-zirconium-tantalum are formed over a semiconductor substrate, the plurality of layers are patterned, and multiple dielectric layers and conductive materials are deposited over the CZT material. Another layer of CZT material encapsulates the conductive material.

公开(公告)号：US10020276B2

公开(公告)日：2018-07-10

申请号：US15346493

申请日：2016-11-08

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chen-Shien Chen ,  Yu-Feng Chen ,  Yu-Wei Lin ,  Tin-Hao Kuo ,  Yu-Min Liang ,  Chun-Hung Lin

IPC: H01L21/00 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48

CPC classification number: H01L24/16 ,  H01L21/481 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/13 ,  H01L2224/13016 ,  H01L2224/13082 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/81

Abstract: An embodiment apparatus includes a dielectric layer in a die, a conductive trace in the dielectric layer, and a protrusion bump pad on the conductive trace. The protrusion bump pad at least partially extends over the dielectric layer, and the protrusion bump pad includes a lengthwise axis and a widthwise axis. A ratio of a first dimension of the lengthwise axis to a second dimension of the widthwise axis is about 0.8 to about 1.2.

公开(公告)号：US09991218B2

公开(公告)日：2018-06-05

申请号：US15498659

申请日：2017-04-27

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shang-Yun Tu ,  Yao-Chun Chuang ,  Ming Hung Tseng ,  Chen-Cheng Kuo ,  Chen-Shien Chen

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L24/16 ,  H01L23/3114 ,  H01L23/3192 ,  H01L23/49811 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/061 ,  H01L2224/06132 ,  H01L2224/13014 ,  H01L2224/13022 ,  H01L2224/13027 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13541 ,  H01L2224/1405 ,  H01L2224/141 ,  H01L2224/16105 ,  H01L2224/16237 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/01047 ,  H01L2924/206 ,  H01L2224/05552

Abstract: A die includes a substrate, a metal pad over the substrate, and a passivation layer covering edge portions of the metal pad. A metal pillar is formed over the metal pad. A portion of the metal pillar overlaps a portion of the metal pad. A center of the metal pillar is misaligned with a center of the metal pad.

公开(公告)号：US20180047690A1

公开(公告)日：2018-02-15

申请号：US15729052

申请日：2017-10-10

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yao-Chun Chuang ,  Chita Chuang ,  Chen-Shien Chen ,  Ming Hung Tseng

IPC: H01L23/00 ,  H01L23/498

Abstract: A package structure includes a chip attached to a substrate. The chip includes a bump structure including a conductive pillar having a length (L) measured along a long axis of the conductive pillar and a width (W) measured along a short axis of the conductive pillar. The substrate includes a pad region and a mask layer overlying the pad region, wherein the mask layer has an opening exposing a portion of the pad region. The chip is attached to the substrate to form an interconnection between the conductive pillar and the pad region. The opening has a first dimension (d1) measured along the long axis and a second dimension (d2) measured along the short axis. In an embodiment, L is greater than d1, and W is less than d2.

公开(公告)号：US20180019149A1

公开(公告)日：2018-01-18

申请号：US15715839

申请日：2017-09-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yung-Jean Lu ,  Ming-Fa Chen ,  Chen-Shien Chen ,  Jao Sheng Huang

IPC: H01L21/683

CPC classification number: H01L21/6833 ,  Y10T29/49124

Abstract: A system and method for a semiconductor wafer carrier is disclosed. An embodiment comprises a semiconductor wafer carrier wherein conductive dopants are implanted into the carrier in order to amplify the coulombic forces between an electrostatic chuck and the carrier to compensate for reduced forces that result from thinner semiconductor wafers. Another embodiment forms conductive layers and vias within the carrier instead of implanting conductive dopants.

公开(公告)号：US09871013B2

公开(公告)日：2018-01-16

申请号：US14584748

申请日：2014-12-29

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Pei-Chun Tsai ,  Yu-Feng Chen ,  Tin-Hao Kuo ,  Chen-Shien Chen ,  Yu-Chih Huang ,  Sheng-Yu Wu

IPC: H01L23/48 ,  H01L29/40 ,  H01L23/52 ,  H01L23/00 ,  H01L23/14 ,  H01L23/498 ,  H05K1/11

CPC classification number: H01L24/17 ,  H01L23/147 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/0401 ,  H01L2224/16057 ,  H01L2224/16113 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2924/15311 ,  H01L2924/15313 ,  H05K1/111 ,  H05K2201/0969 ,  H05K2201/10378 ,  H05K2201/10674 ,  Y02P70/611

Abstract: A package component includes a dielectric layer and a metal pad over the dielectric layer. A plurality of openings is disposed in the metal pad. The first plurality of openings is separated from each other by portions of the metal pad, with the portions of the metal pad interconnected to form a continuous metal region.

公开(公告)号：US20170345677A1

公开(公告)日：2017-11-30

申请号：US15679348

申请日：2017-08-17

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hao-Juin Liu ,  Chita Chuang ,  Yao-Chun Chuang ,  Ming Hung Tseng ,  Chen-Shien Chen

IPC: H01L21/48 ,  H05K1/02 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H05K1/11 ,  H01L23/13

Abstract: A device includes a plurality of first pads in a package substrate, wherein at least one first pad is of a first elongated shape, a plurality of vias in a dielectric layer and over the plurality of first pads, and a plurality of second pads over the package substrate, wherein at least one second pad is of a second elongated shape, and wherein the plurality of second pads is over a top surface of the dielectric layer and placed in a first region, a second region, a third region and a fourth region, and wherein second pads in two contiguous regions are oriented in two different directions.

公开(公告)号：US20170309588A1

公开(公告)日：2017-10-26

申请号：US15646721

申请日：2017-07-11

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Sheng-Yu Wu ,  Tin-Hao Kuo ,  Chita Chuang ,  Chen-Shien Chen

IPC: H01L23/00 ,  H01L23/522 ,  H01L23/532 ,  H01L21/56 ,  H01L23/58 ,  H01L23/31 ,  H01L21/60

CPC classification number: H01L24/17 ,  H01L21/563 ,  H01L23/3171 ,  H01L23/522 ,  H01L23/53238 ,  H01L23/562 ,  H01L23/585 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/81 ,  H01L2021/60255 ,  H01L2224/0345 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05005 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05186 ,  H01L2224/05541 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05582 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05671 ,  H01L2224/05684 ,  H01L2224/06102 ,  H01L2224/1146 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/141 ,  H01L2224/14152 ,  H01L2224/14179 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/17104 ,  H01L2224/17517 ,  H01L2224/73204 ,  H01L2224/81007 ,  H01L2224/81101 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/83104 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/35 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/206 ,  H01L2924/00

Abstract: A device includes a metal pad over a substrate. A passivation layer includes a portion over the metal pad. A post-passivation interconnect (PPI) is electrically coupled to the metal pad, wherein the PPI comprises a portion over the metal pad and the passivation layer. A polymer layer is over the PPI. A dummy bump is over the polymer layer, wherein the dummy bump is electrically insulated from conductive features underlying the polymer layer.

公开(公告)号：US20170236763A1

公开(公告)日：2017-08-17

申请号：US15584864

申请日：2017-05-02

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chen-Hua Yu ,  Tsung-Ding Wang ,  Chen-Shien Chen ,  Chung-Shi Liu ,  Jiun Yi Wu

IPC: H01L23/16 ,  H01L25/18 ,  H01L23/498 ,  H01L23/31

CPC classification number: H01L23/16 ,  H01L21/563 ,  H01L21/764 ,  H01L23/295 ,  H01L23/3128 ,  H01L23/315 ,  H01L23/36 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/80 ,  H01L24/92 ,  H01L25/105 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/80895 ,  H01L2224/92125 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/18161 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A device includes a bottom package component that includes a bottom die, and a dam over a top surface of the bottom die. The dam has a plurality of sides forming a partial ring, with an air gap surrounded by the plurality of side portions. The air gap overlaps the bottom die. A top package component is bonded to the bottom package component, wherein the air gap separates a bottom surface of the top package component from the bottom die.

公开(公告)号：US20170229421A1

公开(公告)日：2017-08-10

申请号：US15497408

申请日：2017-04-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yu-Jen Tseng ,  Yen-Liang Lin ,  Tin-Hao Kuo ,  Chen-Shien Chen ,  Mirng-Ji Lii

IPC: H01L23/00

CPC classification number: H01L24/15 ,  H01L21/02118 ,  H01L21/0273 ,  H01L21/283 ,  H01L21/44 ,  H01L21/47 ,  H01L21/563 ,  H01L23/3142 ,  H01L23/3192 ,  H01L23/488 ,  H01L23/49816 ,  H01L23/5283 ,  H01L24/03 ,  H01L24/10 ,  H01L24/11 ,  H01L24/12 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L2224/02333 ,  H01L2224/0347 ,  H01L2224/0401 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/1146 ,  H01L2224/11472 ,  H01L2224/13005 ,  H01L2224/13012 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13015 ,  H01L2224/13017 ,  H01L2224/13022 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13166 ,  H01L2224/13565 ,  H01L2224/1357 ,  H01L2224/13686 ,  H01L2224/16058 ,  H01L2224/16238 ,  H01L2224/73104 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81345 ,  H01L2224/81815 ,  H01L2224/8182 ,  H01L2224/83104 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2924/00014 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/3841 ,  H01L2224/11 ,  H01L2924/00012 ,  H01L2924/207 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2224/05552 ,  H01L2924/00

Abstract: Semiconductor devices, methods of manufacture thereof, and packaged semiconductor devices are disclosed. A method of forming a device includes forming a conductive trace over a first substrate, the conductive trace having first tapering sidewalls, forming a conductive bump over a second substrate, the conductive bump having second tapering sidewalls and a first surface distal the second substrate, and attaching the conductive bump to the conductive trace via a solder region. The solder region extends from the first surface of the conductive bump to the first substrate, and covers the first tapering sidewalls of the conductive trace. The second tapering sidewalls of the conductive bump are free of the solder region.