公开(公告)号：US20160056250A1

公开(公告)日：2016-02-25

申请号：US14481987

申请日：2014-09-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry Hak-Lay Chuang ,  Wei Cheng Wu ,  Shih-Chang Liu ,  Ya-Chen Kao

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/792 ,  H01L27/115 ,  H01L27/105

CPC classification number: H01L29/42344 ,  H01L27/11573 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66833 ,  H01L29/7833 ,  H01L29/792

Abstract: Some embodiments of the present disclosure provide an integrated circuit (IC) for an embedded flash memory device. The IC includes a flash memory cell having a memory cell gate. A silicide contact pad is arranged in a recess of the memory cell gate. A top surface of the silicide contact pad is recessed relative to a top surface of the memory cell gate. Dielectric side-wall spacers extend along sidewalls of the recess from the top surface of the memory cell gate to the top surface of the silicide contact pad.

Abstract translation: 本公开的一些实施例提供了一种用于嵌入式闪存设备的集成电路（IC）。 IC包括具有存储单元门的闪存单元。 硅化物接触焊盘设置在存储单元栅极的凹部中。 硅化物接触焊盘的顶表面相对于存储单元栅极的顶表面凹陷。 电介质侧壁间隔物从凹槽的侧壁从存储单元栅极的顶表面延伸到硅化物接触焊盘的顶表面。

公开(公告)号：US20150206891A1

公开(公告)日：2015-07-23

申请号：US14161372

申请日：2014-01-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Harry Hak-Lay CHUANG ,  Wei-Cheng WU ,  Ya-Chen Kao

IPC: H01L27/115 ,  H01L21/28 ,  H01L29/423

CPC classification number: H01L27/1157 ,  H01L21/28282 ,  H01L27/11573 ,  H01L29/42332 ,  H01L29/4234 ,  H01L29/42344 ,  H01L29/66545 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/792

Abstract: The present disclosure provides a semiconductor device and a method for manufacturing the same. The semiconductor device includes a substrate, at least one split gate memory device, and at least one logic device. The split gate memory device is disposed on the substrate. The logic device is disposed on the substrate. At least one of a select gate and a main gate of the split gate memory device and a logic gate of the logic device are made of metal. The method for manufacturing the semiconductor device includes forming at least one split gate stack and at least one logic gate stack and respectively replacing at least one of a dummy gate layer and a main gate layer in the split gate stack and the dummy gate layer in the logic gate stack with at least one metal memory gate and a metal logic gate.

Abstract translation: 本发明提供一种半导体器件及其制造方法。 半导体器件包括衬底，至少一个分离栅极存储器件和至少一个逻辑器件。 分离栅极存储器件设置在衬底上。 逻辑器件设置在衬底上。 分离栅极存储器件的选择栅极和主栅极中的至少一个以及逻辑器件的逻辑门由金属制成。 半导体器件的制造方法包括形成至少一个分离栅极堆叠和至少一个逻辑门极堆叠，并且分别替代分离栅极堆叠中的伪栅极层和主栅极层中的至少一个以及虚拟栅极层中的至少一个 具有至少一个金属存储器栅极和金属逻辑门的逻辑门极堆叠。

公开(公告)号：US09659953B2

公开(公告)日：2017-05-23

申请号：US14324369

申请日：2014-07-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Wei Cheng Wu ,  Ya-Chen Kao ,  Yi Hsien Lu

IPC: H01L27/115 ,  H01L21/8234 ,  H01L27/092 ,  H01L29/66 ,  H01L29/423 ,  H01L27/11573 ,  H01L29/51 ,  H01L27/088

CPC classification number: H01L27/11573 ,  H01L21/823462 ,  H01L27/088 ,  H01L27/092 ,  H01L29/42344 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656

Abstract: The present disclosure relates to a structure and method for embedding a non-volatile memory (NVM) in a HKMG (high-κ metal gate) integrated circuit which includes a high voltage (HV) HKMG transistor. NVM devices (e.g., flash memory) are operated at high voltages for its read and write operations and hence a HV device is necessary for integrated circuits involving non-volatile embedded memory and HKMG logic circuits. Forming a HV HKMG circuit along with the HKMG periphery circuit reduces the need for additional boundaries between the HV transistor and rest of the periphery circuit. This method further helps reduce divot issue and reduce cell size.

公开(公告)号：US09627392B2

公开(公告)日：2017-04-18

申请号：US14609575

申请日：2015-01-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Chin-Yi Huang ,  Ya-Chen Kao

IPC: H01L27/115 ,  H01L21/3213 ,  H01L21/321 ,  H01L21/762 ,  H01L29/06 ,  H01L21/28 ,  H01L27/11521 ,  H01L29/66

CPC classification number: H01L27/11507 ,  H01L21/28273 ,  H01L21/32115 ,  H01L21/3212 ,  H01L21/32139 ,  H01L21/76229 ,  H01L27/11521 ,  H01L29/0649 ,  H01L29/66825

Abstract: The present disclosure relates an integrated circuit (IC) for an embedded flash memory device. In some embodiments, the IC includes a memory array region and a boundary region surrounding the memory array region disposed over a semiconductor substrate. A hard mask is disposed at the memory array region comprising a plurality of discrete portions. The hard mask is disposed under a control dielectric layer of the memory array region.

公开(公告)号：US20160181268A1

公开(公告)日：2016-06-23

申请号：US14580454

申请日：2014-12-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Wei Cheng Wu ,  Ya-Chen Kao ,  Shih-Chang Liu ,  Fang-Lan Chu

IPC: H01L27/115

CPC classification number: H01L27/11573 ,  H01L21/823842 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/11526 ,  H01L27/11531 ,  H01L27/11548 ,  H01L27/11575 ,  H01L29/517 ,  H01L29/66545

Abstract: The present disclosure relates to a structure and method for reducing CMP dishing in integrated circuits. In some embodiments, the structure has a semiconductor substrate with an embedded memory region and a periphery region. one or more dummy structures are formed between the memory region and the periphery region. Placement of the dummy structures between the embedded memory region and the periphery region causes the surface of a deposition layer therebetween to become more planar after being polished without resulting in a dishing effect. The reduced recess reduces metal residue formation and thus leakage and shorting of current due to metal residue. Further, less dishing will reduce the polysilicon loss of active devices. In some embodiments, one of the dummy structures is formed with an angled sidewall which eliminates the need for a boundary cut etch process.

Abstract translation: 本公开涉及用于减少集成电路中的CMP凹陷的结构和方法。 在一些实施例中，该结构具有具有嵌入的存储区域和外围区域的半导体衬底。 在存储区域和外围区域之间形成一个或多个虚拟结构。 在嵌入的存储区域和外围区域之间的虚拟结构的放置使得其之间的沉积层的表面在抛光之后变得更平坦，而不会产生凹陷效应。 减少的凹陷减少金属残留物的形成，从而导致金属残留物导致的电流泄漏和短路。 此外，较少的凹陷将减少有源器件的多晶硅损耗。 在一些实施例中，虚拟结构之一形成有成角度的侧壁，其消除了对边界切割蚀刻工艺的需要。

公开(公告)号：US20160005756A1

公开(公告)日：2016-01-07

申请号：US14324369

申请日：2014-07-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Wei Cheng Wu ,  Ya-Chen Kao ,  Yi Hsien Lu

IPC: H01L27/115 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/11573 ,  H01L21/823462 ,  H01L27/088 ,  H01L27/092 ,  H01L29/42344 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656

Abstract: The present disclosure relates to a structure and method for embedding a non-volatile memory (NVM) in a HKMG (high-κ metal gate) integrated circuit which includes a high voltage (HV) HKMG transistor. NVM devices (e.g., flash memory) are operated at high voltages for its read and write operations and hence a HV device is necessary for integrated circuits involving non-volatile embedded memory and HKMG logic circuits. Forming a HV HKMG circuit along with the HKMG periphery circuit reduces the need for additional boundaries between the HV transistor and rest of the periphery circuit. This method further helps reduce divot issue and reduce cell size.

Abstract translation: 本公开涉及一种用于在包括高电压（HV）HKMG晶体管的HKMG（高金属栅极）集成电路中嵌入非易失性存储器（NVM）的结构和方法。 NVM设备（例如，闪速存储器）在高电压下操作用于其读取和写入操作，因此HV器件对于涉及非易失性嵌入式存储器和HKMG逻辑电路的集成电路是必需的。 与HKMG外围电路一起形成HV HKMG电路减少了HV晶体管与外围电路的其余部分之间的附加边界的需要。 该方法进一步有助于减少divot问题并减少单元大小。

公开(公告)号：US11257816B2

公开(公告)日：2022-02-22

申请号：US16794044

申请日：2020-02-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Harry-Hak-Lay Chuang ,  Wei-Cheng Wu ,  Ya-Chen Kao

IPC: H01L29/66 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/321

Abstract: A semiconductor device includes active gate structures and dummy gate electrodes. The active gate structures are above an active region of a substrate. The dummy gate electrodes are above the active region of the substrate. A number of the dummy gate electrodes is less than a number of the active gate structures. The active gate structures and the dummy gate electrodes have different materials, and a distance between adjacent one of the dummy gate electrodes and one of the active gate structures is substantially the same as a gate pitch of the active gate structures.

公开(公告)号：US20210183880A1

公开(公告)日：2021-06-17

申请号：US17184953

申请日：2021-02-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Wei Cheng Wu ,  Ya-Chen Kao ,  Yi Hsien Lu

IPC: H01L27/11573 ,  H01L29/66 ,  H01L29/423 ,  H01L29/51 ,  H01L21/8234 ,  H01L27/092

Abstract: The present disclosure relates to an integrated circuit that includes a semiconductor substrate having a periphery region and memory cell region separated by a boundary region. A pair of split gate flash memory cells are disposed on the memory cell region and include a first select gate and a first memory gate. A first gate electrode is disposed over a first gate dielectric layer on the periphery region. A second gate electrode is disposed over a second gate dielectric layer on the periphery region at a position between the boundary region and the first gate electrode. The second dielectric layer is thicker than the first gate dielectric layer. The first select gate and the first memory gate have upper surfaces that are co-planar or level with the upper surface of the second gate electrode.

公开(公告)号：US10658373B2

公开(公告)日：2020-05-19

申请号：US16055357

申请日：2018-08-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Harry-Hak-Lay Chuang ,  Wei-Cheng Wu ,  Ya-Chen Kao

IPC: H01L27/11568 ,  H01L29/66 ,  H01L27/11573 ,  H01L29/423 ,  H01L29/51 ,  H01L21/8238

Abstract: A method for manufacturing a semiconductor device is provided. The method includes forming a split gate stack having a main gate and a select gate and forming a logic gate stack having a logic gate over a semiconductor substrate. The main gate and the logic gate is respectively replaced with a metal memory gate and a metal logic gate, in which the main gate and the logic gate are replaced simultaneously.

公开(公告)号：US20200020601A1

公开(公告)日：2020-01-16

申请号：US16578303

申请日：2019-09-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Chih-Ren Hsieh ,  Ya-Chen Kao ,  Chen-Chin Liu ,  Chih-Pin Huang

IPC: H01L21/66 ,  H01L27/11529 ,  H01L27/11524

Abstract: Various embodiments of the present application are directed to an integrated circuit (IC) comprising a floating gate test device with a cell-like top layout, as well as a method for forming the IC. In some embodiments, the IC comprises a semiconductor substrate and the floating gate test device. The floating gate test device is on the semiconductor substrate, and comprises a floating gate electrode and a control gate electrode overlying the floating gate electrode. The floating gate electrode and the control gate electrode partially define an array of islands, and further partially define a plurality of bridges interconnecting the islands. The islands and the bridges define the cell-like top layout and may, for example, prevent process-induced damage to the floating gate test device.