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    Multiple-Gate Semiconductor Device and Method
    23.
    发明申请
    Multiple-Gate Semiconductor Device and Method 审中-公开
    多栅极半导体器件及方法

    公开(公告)号：US20150079753A1

    公开(公告)日：2015-03-19

    申请号：US14552237

    申请日：2014-11-24

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Tung Ying Lee ,  Li-Wen Weng ,  Chien-Tai Chan ,  Da-Wen Lin ,  Hsien-Chin Lin

    IPC: H01L29/66

    CPC classification number: H01L29/66795 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/785

    Abstract: A system and method for manufacturing multiple-gate semiconductor devices is disclosed. An embodiment comprises multiple fins, wherein intra-fin isolation regions extend into the substrate less than inter-fin isolation regions. Regions of the multiple fins not covered by the gate stack are removed and source/drain regions are formed from the substrate so as to avoid the formation of voids between the fins in the source/drain region.

    Abstract translation: 公开了一种用于制造多栅极半导体器件的系统和方法。 一个实施例包括多个散热片，其中散热片内隔离区域延伸到小于鳍间隔离区域的衬底内。 去除未被栅极堆叠覆盖的多个鳍片的区域，并且从衬底形成源极/漏极区域，以避免在源极/漏极区域中的鳍片之间形成空隙。

    SPECIALIZED TRANSISTORS
    24.
    发明申请
    SPECIALIZED TRANSISTORS 有权

    公开(公告)号：US20250063791A1

    公开(公告)日：2025-02-20

    申请号：US18496607

    申请日：2023-10-27

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Tsung-Lin Lee ,  Wei-Yang Lee ,  Ming-Chang Wen ,  Chien-Tai Chan ,  Chih Chieh Yeh ,  Da-Wen Lin

    IPC: H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

    Abstract: Semiconductor structures and methods of fabrication are provided. A method according to the present disclosure includes receiving a workpiece that includes an active region over a substrate and having first semiconductor layers interleaved by second semiconductor layers, and a dummy gate stack over a channel region of the active region, etching source/drain regions of the active region to form source/drain trenches that expose sidewalls of the active region, selectively and partially etching second semiconductor layers to form inner spacer recesses, forming inner spacer features in the inner spacer recesses, forming channel extension features on exposed sidewalls of the first semiconductor layers, forming source/drain features over the source/drain trenches, removing the dummy gate stack, selectively removing the second semiconductor layers to form nanostructures in the channel region, forming a gate structure to wrap around each of the nanostructures. The channel extension features include undoped silicon.

    METHOD AND MULTI-CHANNEL DEVICES WITH ANTI-PUNCH-THROUGH FEATURES
    26.
    发明公开
    METHOD AND MULTI-CHANNEL DEVICES WITH ANTI-PUNCH-THROUGH FEATURES 审中-公开

    公开(公告)号：US20230197820A1

    公开(公告)日：2023-06-22

    申请号：US17834564

    申请日：2022-06-07

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Min Jiao ,  Ji-Yin Tsai ,  Da-Wen Lin ,  Hung-Ju Chou

    IPC: H01L29/423 ,  H01L21/8234 ,  H01L29/66

    CPC classification number: H01L29/42392 ,  H01L21/823418 ,  H01L21/823481 ,  H01L29/66545

    Abstract: The present disclosure provide a method that includes receiving a substrate having a semiconductor surface of a first semiconductor material; forming an APT feature in the substrate; performing a prebaking process to the substrate with a first temperature T1; epitaxially growing an undoped semiconductor layer of the first semiconductor layer and a first thickness t1 on the substrate at a second temperature T2; epitaxially growing a semiconductor layer stack over the undoped semiconductor layer at a third temperature T3 less than T2, wherein the semiconductor layer stack includes first semiconductor layers and second semiconductor layers stacked vertically in an alternating configuration; patterning the semiconductor substrate, and the semiconductor layer stack to form a trench, thereby defining an active region being adjacent the trench; forming an isolation feature in the trench; selectively removing the second semiconductor layers; and forming a gate structure wrapping around each of the first semiconductor layers.

    Method and Apparatus For Enhancing Channel Strain
    30.
    发明申请
    Method and Apparatus For Enhancing Channel Strain 有权
    用于增强通道应变的方法和装置

    公开(公告)号：US20150340293A1

    公开(公告)日：2015-11-26

    申请号：US14815375

    申请日：2015-07-31

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Ming-Lung Cheng ,  Da-Wen Lin ,  Yen-Chun Lin

    IPC: H01L21/8238 ,  H01L21/324 ,  H01L29/51 ,  H01L21/02 ,  H01L29/165 ,  H01L29/78

    CPC classification number: H01L29/66795 ,  H01L21/02532 ,  H01L21/02664 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/165 ,  H01L29/511 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7847 ,  H01L29/7848

    Abstract: Various methods include providing a substrate, forming a projection extending upwardly from the substrate, the projection having a channel region therein, and forming a gate structure engaging the projection adjacent to the channel region, the gate structure having spaced first and second conductive layers and a strain-inducing conductive layer disposed between the first and second conductive layers. The method also includes forming epitaxial growths on portions of the projection at each side of the gate structure, the epitaxial growths imparting a first strain to the channel region, and imparting a second strain to the channel region, including performing at least one stress memorization technique on the gate structure such that the strain-inducing conductive layer imparts the second strain to the channel region, and removing the capping layer, wherein the imparting the second strain is carried out in a manner that imparts tensile strain to the channel region.

    Abstract translation: 各种方法包括提供基板，形成从基板向上延伸的突起，突起在其中具有通道区域，以及形成接合邻近通道区域的突起的栅极结构，栅极结构具有间隔开的第一和第二导电层以及 应变诱发导电层设置在第一和第二导电层之间。 所述方法还包括在所述栅极结构的每一侧的所述突起的部分上形成外延生长，所述外延生长对所述沟道区赋予第一应变，并且向所述沟道区赋予第二应变，包括执行至少一个应力记忆技术 在栅极结构上使得应变诱导导电层将第二应变施加到沟道区，并且去除覆盖层，其中赋予第二应变以赋予沟道区的拉伸应变的方式进行。

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