公开(公告)号：US09960232B2

公开(公告)日：2018-05-01

申请号：US15340775

申请日：2016-11-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Borna Obradovic ,  Titash Rakshit ,  Mark Rodder

IPC: H01L29/00 ,  H01L29/06 ,  H01L29/417 ,  H01L29/08 ,  H01L29/20 ,  H01L29/10 ,  H01L29/786 ,  H01L29/66 ,  H01L21/306 ,  H01L29/423

CPC classification number: H01L29/0665 ,  H01L21/30612 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/20 ,  H01L29/205 ,  H01L29/267 ,  H01L29/41758 ,  H01L29/42392 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66742 ,  H01L29/7783 ,  H01L29/78621 ,  H01L29/78681

Abstract: A horizontal nanosheet field effect transistor (hNS FET) including source and drain electrodes, a gate electrode between the source and drain electrodes, a first spacer separating the source electrode from the gate electrode, a second spacer separating the drain electrode from the gate electrode, and a channel region under the gate electrode and extending between the source electrode and the drain electrode. The source electrode and the drain electrode each include an extension region. The extension region of the source electrode is under at least a portion of the first spacer and the extension region of the drain electrode is under at least a portion of the second spacer. The hNS FET also includes at least one layer of crystalline barrier material having a first thickness at the extension regions of the source and drain electrodes and a second thickness less than the first thickness at the channel region.

公开(公告)号：US20180053550A1

公开(公告)日：2018-02-22

申请号：US15343182

申请日：2016-11-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Titash Rakshit ,  Borna J. Obradovic

IPC: G11C13/00 ,  G11C11/56

CPC classification number: G11C13/0069 ,  G11C11/54 ,  G11C11/56 ,  G11C13/004 ,  G11C16/0483 ,  G11C16/10 ,  G11C27/00

Abstract: A neuron circuit for use in a neural network is disclosed. The neural network includes a plurality of field effect transistors having confined channels. The sources and drains of the field effect transistors are connected in series. A plurality of input terminals for receiving a plurality of input voltages may be connected to a drain terminal of a corresponding field effect transistor. The threshold voltages of the field effect transistors can be programmed by increasing or decreasing a number of excess minority carriers in the confined channels, thereby programming the resistance presented by the field effect transistor.

公开(公告)号：US20170323941A1

公开(公告)日：2017-11-09

申请号：US15340775

申请日：2016-11-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Borna Obradovic ,  Titash Rakshit ,  Mark Rodder

IPC: H01L29/06 ,  H01L29/786 ,  H01L29/66 ,  H01L29/417 ,  H01L29/20 ,  H01L29/10 ,  H01L29/08 ,  H01L21/306

CPC classification number: H01L29/0665 ,  H01L21/30612 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/20 ,  H01L29/205 ,  H01L29/267 ,  H01L29/41758 ,  H01L29/42392 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66742 ,  H01L29/7783 ,  H01L29/78621 ,  H01L29/78681

Abstract: A horizontal nanosheet field effect transistor (hNS FET) including source and drain electrodes, a gate electrode between the source and drain electrodes, a first spacer separating the source electrode from the gate electrode, a second spacer separating the drain electrode from the gate electrode, and a channel region under the gate electrode and extending between the source electrode and the drain electrode. The source electrode and the drain electrode each include an extension region. The extension region of the source electrode is under at least a portion of the first spacer and the extension region of the drain electrode is under at least a portion of the second spacer. The hNS FET also includes at least one layer of crystalline barrier material having a first thickness at the extension regions of the source and drain electrodes and a second thickness less than the first thickness at the channel region.

公开(公告)号：US09812449B2

公开(公告)日：2017-11-07

申请号：US15158459

申请日：2016-05-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Borna J. Obradovic ,  Titash Rakshit ,  Mark S. Rodder ,  Wei-E Wang

IPC: H01L21/02 ,  H01L27/088 ,  H01L29/06 ,  H01L29/20 ,  H01L29/423 ,  H01L29/49

CPC classification number: H01L27/088 ,  H01L21/82345 ,  H01L21/8252 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/20 ,  H01L29/201 ,  H01L29/4232 ,  H01L29/42392 ,  H01L29/4916 ,  H01L29/4966 ,  H01L29/775 ,  H01L29/778

Abstract: A nanosheet field effect transistor design in which the threshold voltage is adjustable by adjusting the composition of the gate. The channel of the nanosheet field effect transistor may be composed of a III-V semiconductor material, and the gate, which may be separated from the channel by a high dielectric constant dielectric layer, may also be composed of a III-V semiconductor material. Adjusting the composition of the gate may result in a change in the affinity of the gate, in turn resulting in a change in the threshold voltage. In some embodiments the channel is composed, for example, of InxGa1-xAs, with x between 0.23 and 0.53, and the gate is composed of InAs1-yNy with y between 0.0 and 0.4, and the values of x and y may be adjusted to adjust the threshold voltage.

公开(公告)号：US09685564B2

公开(公告)日：2017-06-20

申请号：US15149722

申请日：2016-05-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Rwik Sengupta ,  Mark Stephen Rodder ,  Joon Goo Hong ,  Titash Rakshit

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66

CPC classification number: H01L29/78696 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/778 ,  H01L29/78618 ,  H01L29/78654 ,  H01L29/78684

Abstract: A Gate-All-Around (GAA) Field Effect Transistor (FET) can include a horizontal nanosheet conductive channel structure having a width in a horizontal direction in the GAA FET, a height that is perpendicular to the horizontal direction, and a length that extends in the horizontal direction, where the width of the horizontal nanosheet conductive channel structure defines a physical channel width of the GAA FET. First and second source/drain regions can be located at opposing ends of the horizontal nanosheet conductive channel structure and a unitary gate material completely surrounding the horizontal nanosheet conductive channel structure.

公开(公告)号：US20170148787A1

公开(公告)日：2017-05-25

申请号：US15158459

申请日：2016-05-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Borna J. Obradovic ,  Titash Rakshit ,  Mark S. Rodder ,  Wei-E Wang

IPC: H01L27/088 ,  H01L29/423 ,  H01L29/06 ,  H01L29/49 ,  H01L29/20

CPC classification number: H01L27/088 ,  H01L21/82345 ,  H01L21/8252 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/20 ,  H01L29/201 ,  H01L29/4232 ,  H01L29/42392 ,  H01L29/4916 ,  H01L29/4966 ,  H01L29/775 ,  H01L29/778

Abstract: A nanosheet field effect transistor design in which the threshold voltage is adjustable by adjusting the composition of the gate. The channel of the nanosheet field effect transistor may be composed of a III-V semiconductor material, and the gate, which may be separated from the channel by a high dielectric constant dielectric layer, may also be composed of a III-V semiconductor material. Adjusting the composition of the gate may result in a change in the affinity of the gate, in turn resulting in a change in the threshold voltage. In some embodiments the channel is composed, for example, of InxGa1-xAs, with x between 0.23 and 0.53, and the gate is composed of InAs1-yNy with y between 0.0 and 0.4, and the values of x and y may be adjusted to adjust the threshold voltage.

公开(公告)号：US09614002B1

公开(公告)日：2017-04-04

申请号：US15238720

申请日：2016-08-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ryan M. Hatcher ,  Titash Rakshit ,  Borna J. Obradovic ,  Jorge Kittl ,  Joon Goo Hong

IPC: G11C11/16 ,  H01L27/22

CPC classification number: G11C11/16 ,  G11C11/161 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  H01L27/224 ,  H01L43/08 ,  H01L43/12

Abstract: A bidirectional memory cell includes a write unit and a read unit. The write unit and the read unit each include an MTJ structure having a first and second pinned layers and a free layer. The first and second pinned layers are separated from the free layer by at least one tunnel barrier. The first pinned layer is electrically coupled to a first write line through a first diode. The second pinned layer is electrically connected to a second word line through a second diode. The free layer is electrically coupled to a first bit line. Additionally, the free layer of the read unit is magnetically coupled to the free layer of the write unit.

公开(公告)号：US11769043B2

公开(公告)日：2023-09-26

申请号：US16839043

申请日：2020-04-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Titash Rakshit ,  Malik Aqeel Anwar ,  Ryan Hatcher

IPC: G06T1/20 ,  G06N3/063 ,  G06F17/16 ,  G06N3/04 ,  G06N3/08 ,  G06F18/21

CPC classification number: G06N3/063 ,  G06F17/16 ,  G06F18/21 ,  G06N3/04 ,  G06N3/08

Abstract: A method of pipelining inference of a neural network, which includes an i-th layer (i being an integer greater than zero) and an (i+1)-th layer, includes processing, for a first input image, first i-th values of the i-th layer to generate first (i+1)-th values for the (i+1)-th layer, processing, for the first input image, the first (i+1)-th values of the (i+1)-th layer to generate output values, and concurrently with processing, for the first image, the (i+1)-th values, processing, for a second input image, second i-th values of the i-th layer to generate second (i+1)-th values.

公开(公告)号：US11574193B2

公开(公告)日：2023-02-07

申请号：US16122789

申请日：2018-09-05

Applicant: Samsung Electronics Co., LTD.

Inventor： Borna J. Obradovic ,  Titash Rakshit ,  Jorge A. Kittl ,  Ryan M. Hatcher

IPC: G06N3/08 ,  G06N5/04 ,  G06N3/04

Abstract: A method and system for training a neural network are described. The method includes providing at least one continuously differentiable model of the neural network. The at least one continuously differentiable model is specific to hardware of the neural network. The method also includes iteratively training the neural network using the at least one continuously differentiable model to provide at least one output for the neural network. Each iteration uses at least one output of a previous iteration and a current continuously differentiable model of the at least one continuously differentiable model.

公开(公告)号：US11556768B2

公开(公告)日：2023-01-17

申请号：US16849638

申请日：2020-04-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ryan Hatcher ,  Titash Rakshit ,  Jorge Kittl ,  Dharmendar Palle ,  Joon Goo Hong

IPC: G06N3/063 ,  G06N3/02

Abstract: A method and system are provided. The method includes mapping a binary matrix to an undirected graph form, applying a two-way graph partition algorithm to the mapped binary matrix that minimizes edge cuts between partitions in the mapped binary matrix, applying a greedy algorithm recursively to find a set of row or column permutations that maximizes a transfer of non-zeros from sparse blocks to nonsparse blocks, and sparsifying or densifying the binary matrix according to the applied greedy algorithm.