公开(公告)号：US20240051079A1

公开(公告)日：2024-02-15

申请号：US18296021

申请日：2023-04-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eunkyoung Kim ,  Kiho Bae ,  Hoyoung Kim ,  Boumyoung Park ,  Boun Yoon

IPC: B24B37/005 ,  G05D11/13

CPC classification number: B24B37/0056 ,  G05D11/138 ,  H01L21/31053

Abstract: A chemical mechanical polishing apparatus includes: supply pipes to which a slurry stock solution and a diluent are supplied; flow rate control units, respectively disposed on the supply pipes to control flow rates of the slurry stock solution and the diluent; a mixer connected to the flow rate control units and configured to mix the slurry stock solution and the diluent, supplied from the supply pipes, to prepare a slurry; a slurry storage unit connected to the mixer and configured to store the slurry prepared in the mixer; a slurry supply unit configured to draw out the slurry stored in the slurry storage unit and to supply the slurry to a polishing pad; and a control unit configured to control the flow rate control units to control a mixing ratio of the slurry stock solution and the diluent and a flow rate of the slurry to the polishing pad.

公开(公告)号：US20230371254A1

公开(公告)日：2023-11-16

申请号：US18062169

申请日：2022-12-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Donghoon KWON ,  Hyo-Jung Kim ,  Chungki Min ,  Boun Yoon

IPC: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10

CPC classification number: H01L27/11582 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565

Abstract: A semiconductor device may include a gate stack including insulating patterns and conductive patterns, which are alternately stacked, first block channel structures penetrating the gate stack, second block channel structures penetrating the gate stack, and an isolation structure penetrating the gate stack. The isolation structure may include a block isolation structure, a first word line isolation structure, and a second word line isolation structure. The block isolation structure may include a first side surface connected to a side surface of the first word line isolation structure, and a second side surface connected to a side surface of the second word line isolation structure, and the first block channel structures comprise an intervening channel structure between the first and second side surfaces of the block isolation structure.

公开(公告)号：US11757015B2

公开(公告)日：2023-09-12

申请号：US17196321

申请日：2021-03-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seunghoon Choi ,  Ilyoung Yoon ,  Ilsu Park ,  Kiho Bae ,  Boun Yoon ,  Yooyong Lee

IPC: H01L29/423 ,  H01L29/49 ,  H01L21/8234

CPC classification number: H01L29/4966 ,  H01L21/823443 ,  H01L21/823475 ,  H01L29/42372

Abstract: A semiconductor device including a substrate; a gate structure on the substrate; a gate spacer on a sidewall of the gate structure; and a polishing stop pattern on the gate structure and the gate spacer, the polishing stop pattern including a first portion covering an upper surface of the gate structure and an upper surface of the gate spacer; and a second portion extending from the first portion in a vertical direction substantially perpendicular to an upper surface of the substrate, wherein an upper surface of a central portion of the first portion of the polishing stop pattern is higher than an upper surface of an edge portion of the first portion thereof, and the upper surface of the central portion of the first portion of the polishing stop pattern is substantially coplanar with an upper surface of the second portion thereof.

公开(公告)号：US20230255031A1

公开(公告)日：2023-08-10

申请号：US18047376

申请日：2022-10-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Donghoon Kwon ,  Boun Yoon ,  Kihoon Jang

IPC: H01L27/11573 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11565 ,  H01L27/1157

CPC classification number: H01L27/11573 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11565 ,  H01L27/1157

Abstract: A semiconductor device includes a peripheral circuit structure including a substrate, a circuit element on the substrate, connection patterns electrically connected to the circuit element, and a peripheral insulating structure on the circuit element, a memory cell structure on the peripheral circuit structure, the memory cell structure including interlayer insulating layers and gate electrodes alternately stacked on each other, an upper wiring, and a through-contact plug electrically connecting the upper wiring to an upper connection pattern in, which is in an uppermost position of the connection patterns relative to an upper surface of the substrate providing a base reference surface, wherein the peripheral circuit structure further includes a dam structure on the upper connection pattern, the peripheral insulating structure includes a first insulating layer on the circuit element and a side surface of the upper connection pattern and a second insulating layer, a capping layer, and a third insulating layer sequentially stacked on the first insulating layer, wherein the dam structure passes through the second insulating layer and contacts the upper connection pattern, and wherein the through-contact plug includes a lower portion passing through the dam structure and contacting the upper connection pattern and an upper portion on the lower portion.

公开(公告)号：US20210134806A1

公开(公告)日：2021-05-06

申请号：US16903040

申请日：2020-06-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yanghee Lee ,  Jonghyuk Park ,  Ilyoung Yoon ,  Boun Yoon ,  Heesook Cheon

IPC: H01L27/108

Abstract: A semiconductor device includes a substrate including first and second region, a bit line structure on the first region, key structures on the second region, each key structure having an upper surface substantially coplanar with an upper surface of the bit line structure, a first trench disposed between two adjacent key structures spaced apart from each other in a first direction, a filling pattern in a lower portion of the first trench, the filling pattern having a flat upper surface and including a first conductive material, and a first conductive structure on the flat upper surface of the filling pattern, an upper sidewall of the first trench, and the upper surface of each of the plurality of key structures, the first conductive structure including a second conductive material.

公开(公告)号：US10716755B2

公开(公告)日：2020-07-21

申请号：US16237913

申请日：2019-01-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngbeom Pyon ,  Kichul Park ,  Inkwon Kim ,  Ki Hoon Jang ,  Byoungho Kwon ,  Sangkyun Kim ,  Boun Yoon

IPC: H01L27/112 ,  H01L23/535 ,  H01L23/528 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L21/768 ,  H01L27/11551 ,  H01L27/11578 ,  H01L21/02 ,  H01L23/538 ,  A61K9/06 ,  A61K45/06 ,  A61K9/00 ,  A61K31/197 ,  A61K47/10 ,  A61K47/12 ,  A61K47/20 ,  A61K47/32 ,  A61K47/44

Abstract: A semiconductor device includes a substrate, a peripheral structure, a lower insulating layer, and a stack. The substrate includes a peripheral circuit region and a cell array region. The peripheral structure is on the peripheral circuit region. The lower insulating layer covers the peripheral circuit region and the cell array region and has a protruding portion protruding from a flat portion. The stack is on the lower insulating layer and the cell array region, and includes upper conductive patterns and insulating patterns which are alternately and repeatedly stacked.

公开(公告)号：US09006067B2

公开(公告)日：2015-04-14

申请号：US14146185

申请日：2014-01-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Bo Kyeong Kang ,  Jaeseok Kim ,  Boun Yoon ,  Hoyoung Kim ,  Ilyoung Yoon

IPC: H01L21/8234

CPC classification number: H01L21/823431 ,  H01L21/823456 ,  H01L21/823481

Abstract: A method of fabricating a semiconductor device includes forming first gate patterns on a semiconductor substrate using an etch mask pattern, forming a trench in the semiconductor substrate between the first gate patterns, forming an insulating layer in the trench, such that the insulating layer fills the trench and is disposed on the etch mask pattern, planarizing the insulating layer until a top surface of the etch mask pattern is exposed, etching a portion of the planarized insulating layer to form a device isolation layer in the trench, forming a second gate layer covering the etch mask pattern and disposed on the device isolation pattern, and planarizing the second gate layer until the top surface of the etch mask pattern is exposed, such that a second gate pattern is formed.

Abstract translation: 制造半导体器件的方法包括使用蚀刻掩模图案在半导体衬底上形成第一栅极图案，在第一栅极图案之间的半导体衬底中形成沟槽，在沟槽中形成绝缘层，使得绝缘层填充 沟槽并且设置在蚀刻掩模图案上，使绝缘层平坦化，直到暴露蚀刻掩模图案的顶表面，蚀刻平坦化绝缘层的一部分以在沟槽中形成器件隔离层，形成第二栅极层覆盖层 蚀刻掩模图案并且设置在器件隔离图案上，并且平坦化第二栅极层，直到暴露出蚀刻掩模图案的顶表面，使得形成第二栅极图案。

公开(公告)号：US08889552B2

公开(公告)日：2014-11-18

申请号：US14083654

申请日：2013-11-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangline Park ,  Boun Yoon ,  Jeongnam Han ,  Kee-Sang Kwon ,  Byung-Kwon Cho ,  Wongsang Choi

IPC: H01L21/44 ,  H01L21/8238

CPC classification number: H01L27/092 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L29/161 ,  H01L29/4175 ,  H01L29/45 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517

Abstract: A semiconductor device is manufactured using dual metal silicide layers. The semiconductor device includes a substrate having first and second regions, a first metal gate electrode on the substrate in the first region, a second metal gate electrode on the substrate in the second region, a first epitaxial layer on and in the substrate at both sides of the first metal gate electrode, a second epitaxial layer on and in the substrate at both sides of the second metal gate electrode, a first metal silicide layer on the first epitaxial layer, a second metal silicide layer on the second epitaxial layer, an interlayer dielectric layer on the first and second metal silicide layers, contact plugs passing through the interlayer dielectric layer and electrically connected to the first and second metal silicide layers.

Abstract translation: 使用双金属硅化物层制造半导体器件。 半导体器件包括具有第一和第二区域的衬底，第一区域中的衬底上的第一金属栅电极，第二区域中的衬底上的第二金属栅电极，两侧的衬底上的第一外延层 的第二金属硅化物层，第二外延层上的第二金属硅化物层，第二外延层上的第二金属硅化物层，第二外延层上的第二金属硅化物层，第二外延层上的第二金属硅化物层， 在第一和第二金属硅化物层上的电介质层，通过层间电介质层并电连接到第一和第二金属硅化物层的接触插塞。

公开(公告)号：US08859371B2

公开(公告)日：2014-10-14

申请号：US13795839

申请日：2013-03-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myung Geun Song ,  Ki-Hyung Ko ,  Hayoung Jeon ,  Boun Yoon ,  Jeongnam Han

IPC: H01L21/8234

CPC classification number: H01L29/401 ,  H01L21/823462 ,  H01L29/66545

Abstract: Methods for manufacturing a semiconductor device having a dual gate dielectric layer may include providing a substrate including first and second regions, forming a first gate dielectric layer having a first thickness on the substrate, forming an interlayer insulating layer including first and second trenches exposing the first gate dielectric layer in the first and second regions, forming a sacrificial layer on the interlayer insulating layer and bottoms of the first and second trenches, forming a sacrificial pattern exposing the first gate dielectric layer of the bottom of the first trench, removing the first gate dielectric layer of the bottom of the first trench, forming a second gate dielectric layer having a second thickness on the bottom of the first trench, removing the sacrificial pattern, and forming a gate electrode on each of the first and second gate dielectric layers.

Abstract translation: 制造具有双栅极电介质层的半导体器件的方法可以包括提供包括第一和第二区域的衬底，在衬底上形成具有第一厚度的第一栅极电介质层，形成包括第一和第二沟槽的层间绝缘层， 在所述第一和第二区域中的栅介质层，在所述层间绝缘层和所述第一沟槽和所述第二沟槽的底部上形成牺牲层，形成暴露所述第一沟槽的底部的第一栅极介电层的牺牲图案，去除所述第一栅极 在所述第一沟槽的底部形成介电层，在所述第一沟槽的底部形成具有第二厚度的第二栅极介电层，去除所述牺牲图案，以及在所述第一和第二栅极电介质层中的每一个上形成栅电极。

公开(公告)号：US08841769B2

公开(公告)日：2014-09-23

申请号：US13796195

申请日：2013-03-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangjine Park ,  Boun Yoon ,  Jeongnam Han ,  Kee-Sang Kwon ,  Wonsang Choi

IPC: H01L23/48 ,  H01L23/52 ,  H01L21/44 ,  H01L21/4763 ,  H01L23/485 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/53238 ,  H01L21/76805 ,  H01L21/7682 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76846 ,  H01L21/76852 ,  H01L21/76865 ,  H01L21/76883 ,  H01L23/485 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a first insulating layer on a substrate; a first contact hole passing through the first insulating layer and exposing an upper surface of the substrate; a first barrier metal layer disposed on a sidewall and at a bottom of the first contact hole and a first metal plug disposed on the first barrier metal layer and in the first contact hole. A recess region is between the first insulating layer and the first metal plug. A gap-fill layer fills the recess region; and a second insulating layer is on the gap-fill layer. A second contact hole passes through the second insulating layer and exposes the upper surface of the first metal plug. A second barrier metal layer is on a sidewall and at the bottom of the second contact hole; and a second metal plug is on the second barrier metal layer.

Abstract translation: 半导体器件包括：衬底上的第一绝缘层; 穿过所述第一绝缘层并暴露所述衬底的上表面的第一接触孔; 设置在第一接触孔的侧壁和底部的第一阻挡金属层和设置在第一阻挡金属层上和第一接触孔中的第一金属栓。 凹部区域位于第一绝缘层和第一金属插塞之间。 间隙填充层填充凹部区域; 并且间隙填充层上的第二绝缘层。 第二接触孔穿过第二绝缘层并暴露第一金属插塞的上表面。 第二阻挡金属层位于第二接触孔的侧壁和底部; 并且第二金属塞在第二阻挡金属层上。