公开(公告)号：US20180145062A1

公开(公告)日：2018-05-24

申请号：US15861140

申请日：2018-01-03

Applicant: QUALCOMM Incorporated

Inventor： Je-Hsiung Jeffrey Lan ,  Niranjan Sunil Mudakatte ,  Changhan Hobie Yun ,  Daeik Daniel Kim ,  Chengjie Zuo ,  David Francis Berdy ,  Mario Francisco Velez ,  Jonghae Kim

IPC: H01L27/01 ,  H01L49/02 ,  H01L23/522 ,  H01L23/15

CPC classification number: H01L27/01 ,  H01G2/02 ,  H01G4/005 ,  H01L21/4846 ,  H01L23/15 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/5223 ,  H01L23/5227 ,  H01L28/10 ,  H01L28/75 ,  H01L2224/11

Abstract: A device includes a glass substrate and a capacitor. The capacitor includes a first metal coupled to a first electrode, a dielectric structure, and a via structure comprising a second electrode of the capacitor. The first metal structure is separated from the via structure by the dielectric structure.

公开(公告)号：US09966426B2

公开(公告)日：2018-05-08

申请号：US14853967

申请日：2015-09-14

Applicant: QUALCOMM Incorporated

Inventor： Niranjan Sunil Mudakatte ,  Daeik Daniel Kim ,  David Francis Berdy ,  Changhan Hobie Yun ,  Je-Hsiung Jeffrey Lan ,  Chengjie Zuo ,  Mario Francisco Velez ,  Robert Paul Mikulka ,  Jonghae Kim

IPC: H01L23/057 ,  H01L23/48 ,  H01L23/495 ,  H01L49/02 ,  H01L23/522 ,  H01L27/08 ,  H01L23/00

CPC classification number: H01L28/60 ,  H01L23/5223 ,  H01L24/13 ,  H01L27/0805 ,  H01L28/87 ,  H01L28/91 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/13109 ,  H01L2224/94 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/10337 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2224/03

Abstract: An augmented capacitor structure includes a substrate and a first capacitor plate of a first conductive layer on the substrate. The augmented capacitor structure also includes an insulator layer on a surface of the first capacitor plate facing away from the substrate and a second capacitor plate. The second capacitor plate includes a second conductive layer on the insulator layer, supported by the first capacitor plate as a first capacitor. A second capacitor electrically is coupled in series with the first capacitor. The first capacitor plate is shared by the first capacitor and the second capacitor as a shared first capacitor plate. An extended first capacitor plate includes a first dummy portion of a third conductive layer and a first dummy via bar extending along the surface of the shared first capacitor plate. The first dummy portion extends along and is supported by the first dummy via bar.

公开(公告)号：US09906318B2

公开(公告)日：2018-02-27

申请号：US14682023

申请日：2015-04-08

Applicant: QUALCOMM Incorporated

Inventor： Chengjie Zuo ,  Daeik Daniel Kim ,  David Francis Berdy ,  Changhan Hobie Yun ,  Je-Hsiung Jeffrey Lan ,  Robert Paul Mikulka ,  Mario Francisco Velez ,  Jonghae Kim ,  Matthew Michael Nowak ,  Ryan Scott C. Spring ,  Xiangdong Zhang

IPC: H04J1/00 ,  H04J1/08 ,  H03H7/46 ,  H04B1/00

CPC classification number: H04J1/08 ,  H03H7/465 ,  H03H2240/00 ,  H03H2250/00 ,  H04B1/0057 ,  H04B1/006 ,  H04B1/0064

Abstract: An apparatus is disclosed that includes a frequency multiplexer circuit coupled to an input node and configured to receive an input signal via the input node. The frequency multiplexer circuit comprises a first filter circuit, a second filter circuit, and a third filter circuit. The apparatus also includes a switching circuit that is configurable to couple at least two of a first output of the first filter circuit, a second output of the second filter circuit, or a third output of the third filter circuit to a single output port.

公开(公告)号：US20170331445A1

公开(公告)日：2017-11-16

申请号：US15151351

申请日：2016-05-10

Applicant: QUALCOMM Incorporated

Inventor： Yunfei Ma ,  Chengjie Zuo ,  David Francis Berdy ,  Daeik Daniel Kim ,  Changhan Hobie Yun ,  Je-Hsiung Jeffrey Lan ,  Mario Francisco Velez ,  Niranjan Sunil Mudakatte ,  Robert Paul Mikulka ,  Jonghae Kim

IPC: H03H7/38 ,  H03H7/40

CPC classification number: H03H7/38 ,  H03H7/40 ,  H04B1/0458

Abstract: A tunable matching network is disclosed. In a particular example, the matching network includes at least one first inductor in a signal path of the matching network. The matching network includes at least one second inductor outside of the signal path. The matching network includes one or more switches coupled to the at least one second inductor. The one or more switches are configured to selectively enable mutual coupling of the at least one first inductor and the at least one second inductor.

公开(公告)号：US09768109B2

公开(公告)日：2017-09-19

申请号：US14861958

申请日：2015-09-22

Applicant: QUALCOMM Incorporated

Inventor： Shiqun Gu ,  Daeik Daniel Kim ,  Matthew Michael Nowak ,  Jonghae Kim ,  Changhan Hobie Yun ,  Je-Hsiung Jeffrey Lan ,  David Francis Berdy

IPC: H01L23/498 ,  H01L21/84 ,  H01L21/8234 ,  H01L21/304 ,  H01L27/088 ,  H01L27/12 ,  H01L23/66 ,  H01L21/306

CPC classification number: H01L27/1203 ,  H01L21/304 ,  H01L21/30604 ,  H01L21/76251 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/823481 ,  H01L21/84 ,  H01L23/49894 ,  H01L23/528 ,  H01L23/66 ,  H01L27/088 ,  H01L27/092 ,  H01L27/1222 ,  H01L27/1248 ,  H01L27/1255 ,  H01L27/1266 ,  H01L29/1087 ,  H01L29/66772

Abstract: An integrated circuit (IC) includes a first semiconductor device on a glass substrate. The first semiconductor device includes a first semiconductive region of a bulk silicon wafer. The IC includes a second semiconductor device on the glass substrate. The second semiconductor device includes a second semiconductive region of the bulk silicon wafer. The IC includes a through substrate trench between the first semiconductive region and the second semiconductive region. The through substrate trench includes a portion disposed beyond a surface of the bulk silicon wafer.

公开(公告)号：US20170062120A1

公开(公告)日：2017-03-02

申请号：US14841132

申请日：2015-08-31

Applicant: QUALCOMM Incorporated

Inventor： Changhan Hobie Yun ,  Mario Francisco Velez ,  Chengjie Zuo ,  Daeik Daniel Kim ,  David Francis Berdy ,  Je-Hsiung Jeffrey Lan ,  Jonghae Kim ,  Niranjan Sunil Mudakatte ,  Robert Paul Mikulka

IPC: H01F27/28 ,  H01F41/14 ,  H01F41/04 ,  H01F27/245

CPC classification number: H01F27/2804 ,  H01F17/0013 ,  H01F17/0033 ,  H01F27/245 ,  H01F41/042 ,  H01F41/046 ,  H01F41/14 ,  H01F41/32 ,  H01F2027/2809 ,  H01L23/645 ,  H01L2224/16225 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/165 ,  H01L2924/00012

Abstract: A substrate includes a first dielectric layer, a magnetic core at least partially in the first dielectric layer, where the magnetic core comprises a first non-horizontal thin film magnetic (TFM) layer. The substrate also includes a first inductor that includes a plurality of first interconnects, where the first inductor is positioned in the substrate to at least partially surround the magnetic core. The magnetic core may further include a second non-horizontal thin film magnetic (TFM) layer. The magnetic core may further include a core layer. The magnetic core may further include a third thin film magnetic (TFM) layer, and a fourth thin film magnetic (TFM) layer that is substantially parallel to the third thin film magnetic (TFM) layer.

Abstract translation: 衬底包括第一介电层，至少部分地在第一介电层中的磁芯，其中磁芯包括第一非水平薄膜磁性（TFM）层。 衬底还包括包括多个第一互连件的第一电感器，其中第一电感器定位在衬底中以至少部分地围绕磁芯。 磁芯还可以包括第二非水平薄膜磁性（TFM）层。 磁芯还可以包括芯层。 磁芯还可以包括第三薄膜磁性（TFM）层和基本上平行于第三薄膜磁性（TFM）层的第四薄膜磁性（TFM）层。

公开(公告)号：US20160095208A1

公开(公告)日：2016-03-31

申请号：US14498230

申请日：2014-09-26

Applicant: QUALCOMM Incorporated

Inventor： Daeik Daniel Kim ,  Je-Hsiung Jeffrey Lan ,  Changhan Hobie Yun ,  Mario Francisco Velez ,  Chengjie Zuo ,  Jonghae Kim ,  David Francis Berdy

IPC: H05K1/02 ,  H01L21/768 ,  H05K1/09 ,  C23F1/02 ,  H05K1/03

CPC classification number: H05K1/0271 ,  C23F1/02 ,  H01L21/768 ,  H01L23/562 ,  H01L2924/0002 ,  H05K1/0306 ,  H05K1/09 ,  H05K2201/0154 ,  H05K2201/0195 ,  H01L2924/00

Abstract: A device includes a stress relief region between at least two stress domains of a substrate (e.g., of a semiconductor die or other integrated circuit). The stress relief region includes a conductive structure electrically coupling circuitries of the stress domains between which the conductive structure is disposed.

Abstract translation: 器件包括在衬底（例如，半导体管芯或其他集成电路）的至少两个应力结构域之间的应力消除区域。 应力消除区域包括导电结构，电耦合应力区域的电路，导电结构设置在该应力区域之间。

公开(公告)号：US20160093750A1

公开(公告)日：2016-03-31

申请号：US14498359

申请日：2014-09-26

Applicant: QUALCOMM Incorporated

Inventor： Daeik Daniel Kim ,  Jonghae Kim ,  Chengjie Zuo ,  Sang-June Park ,  Changhan Hobie Yun ,  Mario Francisco Velez ,  David Francis Berdy ,  Matthew Michael Nowak ,  Robert Paul Mikulka

IPC: H01L29/93

CPC classification number: H01L29/93 ,  H01L27/0629 ,  H01L29/94

Abstract: An apparatus includes a varactor having a first contact that is located on a first side of a substrate. The varactor includes a second contact that is located on a second side of the substrate, and the second side is opposite the first side. The apparatus further includes a signal path between the first contact and the second contact.

Abstract translation: 一种装置包括具有位于衬底的第一侧上的第一接触的变容二极管。 变容二极管包括位于衬底的第二侧上的第二接触件，第二侧面与第一侧相对。 该装置还包括在第一触点和第二触点之间的信号路径。

公开(公告)号：US09202789B2

公开(公告)日：2015-12-01

申请号：US14254764

申请日：2014-04-16

Applicant: QUALCOMM Incorporated

Inventor： Daeik Daniel Kim ,  Mario Francisco Velez ,  Jonghae Kim ,  Matthew Michael Nowak ,  Chengjie Zuo ,  Changhan Hobie Yun ,  David Francis Berdy ,  Robert Paul Mikulka

IPC: H01L23/48 ,  H01L23/552 ,  H01L23/31 ,  H01L23/00 ,  H01L23/498 ,  H01L23/04 ,  H01L23/538 ,  H05K9/00

CPC classification number: H01L23/552 ,  H01L23/04 ,  H01L23/3107 ,  H01L23/32 ,  H01L23/49805 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5386 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16113 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/181 ,  H01R12/7076 ,  H01R12/714 ,  H05K1/181 ,  H05K9/0032 ,  H05K2201/10189 ,  H05K2201/1053 ,  H05K2201/10734 ,  Y02P70/611 ,  H01L2924/014 ,  H01L2924/00014

Abstract: Some novel features pertain to an integrated device package (e.g., die package) that includes a package substrate, a die, an encapsulation layer and a first set of metal layers. The package substrate includes a first surface and a second surface. The die is coupled to the first surface of the package substrate. The encapsulation layer encapsulates the die. The first set of metal layers is coupled to a first exterior surface of the encapsulation layer. In some implementations, the first set of metal layers is configured to operate as a die-to-wire connector of the integrated device package. In some implementations, the integrated device package includes a second set of metal layers coupled to the second surface of the package substrate. In some implementations, the integrated device package includes a second set of metal layers coupled to a second exterior surface of the encapsulation layer.

Abstract translation: 一些新颖特征涉及包括封装衬底，管芯，封装层和第一组金属层的集成器件封装（例如管芯封装）。 封装衬底包括第一表面和第二表面。 模具耦合到封装衬底的第一表面。 封装层封装模具。 第一组金属层耦合到封装层的第一外表面。 在一些实施方案中，第一组金属层被配置为作为集成器件封装的管芯到线连接器工作。 在一些实施方案中，集成器件封装包括耦合到封装衬底的第二表面的第二组金属层。 在一些实施方案中，集成器件封装包括耦合到封装层的第二外表面的第二组金属层。

公开(公告)号：US20150304059A1

公开(公告)日：2015-10-22

申请号：US14682023

申请日：2015-04-08

Applicant: QUALCOMM Incorporated

Inventor： Chengjie Zuo ,  Daeik Daniel Kim ,  David Francis Berdy ,  Changhan Hobie Yun ,  Je-Hsiung Jeffrey Lan ,  Robert Paul Mikulka ,  Mario Francisco Velez ,  Jonghae Kim ,  Matthew Michael Nowak ,  Ryan Scott C. Spring ,  Xiangdong Zhang

IPC: H04J1/08

CPC classification number: H04J1/08 ,  H03H7/465 ,  H03H2240/00 ,  H03H2250/00 ,  H04B1/0057 ,  H04B1/006 ,  H04B1/0064

Abstract: An apparatus is disclosed that includes a frequency multiplexer circuit coupled to an input node and configured to receive an input signal via the input node. The frequency multiplexer circuit comprises a first filter circuit, a second filter circuit, and a third filter circuit. The apparatus also includes a switching circuit that is configurable to couple at least two of a first output of the first filter circuit, a second output of the second filter circuit, or a third output of the third filter circuit to a single output port.

Abstract translation: 公开了一种装置，其包括耦合到输入节点并经配置以经由输入节点接收输入信号的频率复用器电路。 频率复用器电路包括第一滤波器电路，第二滤波器电路和第三滤波器电路。 该装置还包括可配置为将第一滤波器电路的第一输出，第二滤波器电路的第二输出或第三滤波器电路的第三输出中的至少两个耦合到单个输出端口的开关电路。