公开(公告)号：US20170207313A1

公开(公告)日：2017-07-20

申请号：US15213879

申请日：2016-07-19

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul Song ,  Jeffrey Junhao Xu ,  Kern Rim ,  Da Yang ,  Peijie Feng ,  Choh Fei Yeap

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/42392 ,  H01L29/0673 ,  H01L29/66439 ,  H01L29/66484 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7831 ,  H01L29/785

Abstract: Nanowire metal-oxide semiconductor (MOS) Field-Effect Transistors (FETs) (MOSFETs) employing a nanowire channel structure employing recessed conductive structures for conductively coupling nanowire structures are disclosed. Conductive structures are disposed between adjacent nanowire structures to conductively couple nanowire structures. Providing conductive structures in the nanowire channel structure increases the average cross-sectional area of nanowire structures, as compared to a similar nanowire channel structure not employing conductive structures, thus increasing effective channel width and drive strength for a given channel structure height. The precision of a gate material filling process is also eased, because gate material does not have to be disposed in areas between adjacent nanowire structures occupied by conductive structures. The conductive structure width can also be recessed with regard to width of nanowire structures in the nanowire channel structure to allow for a thicker metal gate to lower the gate resistance, while providing excellent electrostatic gate control of the channel.

公开(公告)号：US09653399B2

公开(公告)日：2017-05-16

申请号：US14622516

申请日：2015-02-13

Applicant: QUALCOMM Incorporated

Inventor： John Jianhong Zhu ,  Da Yang ,  Jeffrey Junhao Xu ,  Stanley Seungchul Song ,  Kern Rim

IPC: H01L23/52 ,  H01L23/532 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/311 ,  H01L21/768 ,  H01L23/528 ,  H01L23/535 ,  H01L23/522

CPC classification number: H01L23/53295 ,  H01L21/02178 ,  H01L21/31111 ,  H01L21/76802 ,  H01L21/7681 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823871 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53257 ,  H01L23/535

Abstract: An electronic device includes a middle-of-line (MOL) stack. The electronic device includes a top local interconnect layer and a contact coupling the top local interconnect layer to a gate of a semiconductor device through a first dielectric layer. The electronic device also includes one or more isolation walls between the contact and the first dielectric layer, wherein the one or more isolation walls include aluminum nitride (AlN).

公开(公告)号：US20160293485A1

公开(公告)日：2016-10-06

申请号：US14853670

申请日：2015-09-14

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul Song ,  Jeffrey Junhao Xu ,  Kern Rim ,  Da Yang ,  John Jianhong Zhu ,  Junjing Bao ,  Niladri Narayan Mojumder ,  Vladimir Machkaoutsan ,  Mustafa Badaroglu ,  Choh Fei Yeap

IPC: H01L21/768 ,  H01L21/3213 ,  H01L23/535 ,  H01L27/088 ,  H01L21/8234

CPC classification number: H01L21/76897 ,  H01L21/32139 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76895 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/535 ,  H01L27/0886 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785

Abstract: A fin-type semiconductor device includes a gate structure and a source/drain structure. The fin-type semiconductor device also includes a gate hardmask structure coupled to the gate structure. The gate hardmask structure comprises a first material. The fin-type semiconductor device further includes a source/drain hardmask structure coupled to the source/drain structure. The source/drain hardmask structure comprises a second material.

Abstract translation: 翅片型半导体器件包括栅极结构和源极/漏极结构。 翅片型半导体器件还包括耦合到栅极结构的栅极硬掩模结构。 门硬掩模结构包括第一材料。 翅片型半导体器件还包括耦合到源极/漏极结构的源极/漏极硬掩模结构。 源极/漏极硬掩模结构包括第二材料。

公开(公告)号：US09263279B2

公开(公告)日：2016-02-16

申请号：US13864344

申请日：2013-04-17

Applicant: QUALCOMM Incorporated

Inventor： John J. Zhu ,  Zhongze Wang ,  Da Yang

IPC: H01L21/28 ,  H01L21/31 ,  H01L21/469 ,  H01L21/283 ,  H01L21/768 ,  H01L23/50 ,  G03F7/20 ,  H01L23/00

CPC classification number: H01L21/76894 ,  G03F7/7045 ,  G03F7/70466 ,  H01L21/28123 ,  H01L21/283 ,  H01L21/31 ,  H01L21/469 ,  H01L21/76892 ,  H01L21/76895 ,  H01L23/50 ,  H01L24/27 ,  H01L24/31 ,  H01L2924/0002 ,  H01L2924/12042 ,  H01L2924/00

Abstract: Features are fabricated on a semiconductor chip. The features are smaller than the threshold of the lithography used to create the chip. A method includes patterning a first portion of a feature (such as a local interconnect) and a second portion of the feature to be separated by a predetermined distance, such as a line tip to tip space or a line space. The method further includes patterning the first portion with a cut mask to form a first sub-portion (e.g., a contact) and a second sub-portion. A dimension of the first sub-portion is less than a dimension of a second predetermined distance, which may be a line length resolution of a lithographic process having a specified width resolution. A feature of a semiconductor device includes a first portion and a second portion having a dimension less than a lithographic resolution of the first portion.

Abstract translation: 特征是在半导体芯片上制造的。 这些特征小于用于制造芯片的光刻的阈值。 一种方法包括图案化特征（例如局部互连）的第一部分和要被分离预定距离的特征的第二部分，例如线尖到尖端空间或线空间。 该方法还包括用切割掩模图案化第一部分以形成第一子部分（例如，接触）和第二子部分。 第一子部分的尺寸小于第二预定距离的尺寸，其可以是具有指定宽度分辨率的光刻工艺的线长分辨率。 半导体器件的特征包括具有小于第一部分的光刻分辨率的尺寸的第一部分和第二部分。

公开(公告)号：US20200303550A1

公开(公告)日：2020-09-24

申请号：US16895909

申请日：2020-06-08

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul Song ,  Kern Rim ,  Da Yang ,  Peijie Feng

IPC: H01L29/78 ,  H01L29/06 ,  H01L27/092 ,  H01L29/66 ,  H01L29/423 ,  H01L21/8238 ,  H01L29/165

Abstract: Cell circuits having a diffusion break with avoided or reduced adjacent semiconductor channel strain relaxation and related methods are disclosed. In one aspect, a cell circuit includes a substrate of semiconductor material and a semiconductor channel structure(s) of a second semiconductor material disposed on the substrate. The semiconductor material applies a stress to the formed semiconductor channel structure(s) to induce a strain in the semiconductor channel structure(s) for increasing carrier mobility. A diffusion break comprising a dielectric material extends through a surrounding structure of an interlayer dielectric, and the semiconductor channel structure(s) and at least a portion of the substrate. The relaxation of strain in areas of the semiconductor channel structure(s) adjacent to the diffusion break is reduced or avoided, because the semiconductor channel structure(s) is constrained by the surrounding structure.

公开(公告)号：US20180301447A1

公开(公告)日：2018-10-18

申请号：US15487664

申请日：2017-04-14

Applicant: QUALCOMM Incorporated

Inventor： John Jianhong Zhu ,  Da Yang ,  Jeffrey Junhao Xu

IPC: H01L27/088 ,  H01L23/528 ,  H01L27/02 ,  H01L29/06 ,  H01L21/8234

Abstract: Metal-oxide semiconductor (MOS) standard cells employing electrically coupled source regions and supply rails to relax source-drain tip-to-tip spacing between adjacent MOS standard cells are disclosed. In one aspect, a MOS standard cell includes supply rails disposed in a first metal layer and along respective axes in an X-axis direction. The MOS standard cell includes metal lines disposed in the first metal layer and along respective axes in the X-axis direction. The MOS standard cell includes a source region formed in a semiconductor substrate beneath the first metal layer and adjacent to a plane in an X-Z-axis direction disposed between a supply rail and the source region. The source region is electrically coupled to the corresponding supply rail. Forming the source region in this manner allows the MOS standard cell to be disposed adjacent to other MOS standard cells while achieving the minimum required source-drain tip-to-tip spacing.

公开(公告)号：US10079293B2

公开(公告)日：2018-09-18

申请号：US15839050

申请日：2017-12-12

Applicant: QUALCOMM Incorporated

Inventor： Jeffrey Junhao Xu ,  Kern Rim ,  John Jianhong Zhu ,  Stanley Seungchul Song ,  Mustafa Badaroglu ,  Vladimir Machkaoutsan ,  Da Yang ,  Choh Fei Yeap

IPC: H01L29/66 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L29/6681 ,  H01L29/4991 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A method includes forming a first spacer structure on a dummy gate of a semiconductor device and forming a sacrificial spacer on the first spacer structure. The method also includes etching a structure of the semiconductor device to create an opening, removing the sacrificial spacer via the opening, and depositing a material to close to define a gap.

公开(公告)号：US10043796B2

公开(公告)日：2018-08-07

申请号：US15097142

申请日：2016-04-12

Applicant: QUALCOMM Incorporated

Inventor： Vladimir Machkaoutsan ,  Stanley Seungchul Song ,  Mustafa Badaroglu ,  John Jianhong Zhu ,  Junjing Bao ,  Jeffrey Junhao Xu ,  Da Yang ,  Matthew Michael Nowak ,  Choh Fei Yeap

IPC: H01L29/06 ,  H01L27/088 ,  H01L27/02 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/423 ,  H01L27/06

Abstract: A device includes a substrate, a first nanowire field effect transistor (FET), and a second nanowire FET positioned between the substrate and the first nanowire FET. The device also includes a first nanowire electrically coupled to the first nanowire FET and to the second nanowire FET.

公开(公告)号：US20180076189A1

公开(公告)日：2018-03-15

申请号：US15266523

申请日：2016-09-15

Applicant: QUALCOMM Incorporated

Inventor： Jeffrey Junhao Xu ,  Mustafa Badaroglu ,  Da Yang

IPC: H01L27/02 ,  H01L29/423 ,  G06F17/50

CPC classification number: H01L27/0207 ,  G06F17/5068 ,  G06F17/5072 ,  G06F17/5077 ,  H01L27/11807 ,  H01L29/4232 ,  H01L2027/11811

Abstract: Minimum track standard cell circuits for reduced area are provided. In one aspect, a minimum track standard cell circuit employs a first high aspect ratio voltage rail disposed over a first one-half track and configured to provide a first voltage (e.g., VDD) to the minimum track standard cell circuit. A second high aspect ratio voltage rail is disposed over a second one-half track substantially parallel to the first high aspect ratio voltage rail. The second high aspect ratio voltage rail is configured to provide a second voltage less than the first voltage (e.g., VSS) to the minimum track standard cell circuit. The minimum track standard cell circuit employs multiple tracks disposed between the first and second one-half tracks. The number of tracks can be limited based on particular factors. Minimizing tracks reduces area compared to conventional standard cell circuits.

公开(公告)号：US20170221884A1

公开(公告)日：2017-08-03

申请号：US15097142

申请日：2016-04-12

Applicant: QUALCOMM Incorporated

Inventor： Vladimir Machkaoutsan ,  Stanley Seungchul Song ,  Mustafa Badaroglu ,  John Jianhong Zhu ,  Junjing Bao ,  Jeffrey Junhao Xu ,  Da Yang ,  Matthew Michael Nowak ,  Choh Fei Yeap

IPC: H01L27/088 ,  H01L29/06 ,  H01L21/8234 ,  H01L27/02

CPC classification number: H01L27/088 ,  H01L21/823418 ,  H01L21/823475 ,  H01L21/823481 ,  H01L21/823487 ,  H01L21/823885 ,  H01L27/0207 ,  H01L27/0688 ,  H01L29/0649 ,  H01L29/0669 ,  H01L29/0676 ,  H01L29/42392

Abstract: A device includes a substrate, a first nanowire field effect transistor (FET), and a second nanowire FET positioned between the substrate and the first nanowire FET. The device also includes a first nanowire electrically coupled to the first nanowire FET and to the second nanowire FET.