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公开(公告)号：US20180020548A1
公开(公告)日：2018-01-18
申请号：US15209244
申请日：2016-07-13
Applicant: General Electric Company
Inventor： Christopher James Kapusta , Kaustubh Ravindra Nagarkar
IPC: H05K1/18 , H01L23/31 , H01L23/538 , H01L23/66 , H05K3/32 , H01L23/00 , H05K1/02 , H01L21/48 , H01M10/0585 , H05K3/40 , H01L21/56 , H05K1/11
CPC classification number: H05K1/185 , H01L21/486 , H01L21/565 , H01L23/3121 , H01L23/5383 , H01L23/5384 , H01L23/5389 , H01L23/58 , H01L23/66 , H01L24/00 , H01L24/19 , H01L24/20 , H01L24/32 , H01L24/83 , H01L25/16 , H01L2223/6677 , H01L2224/04105 , H01L2224/24137 , H01L2224/32225 , H01L2224/83192 , H01L2224/92144 , H01L2924/1421 , H01L2924/1461 , H01M2/20 , H01M6/40 , H01M10/0436 , H01M10/052 , H01M10/0562 , H01M10/0585 , H01M10/0587 , H01M10/425 , H01M2220/30 , H04W4/70 , H05K1/0298 , H05K1/115 , H05K3/32 , H05K3/4038 , H05K2201/10037 , H05K2201/10098 , H05K2201/10151 , H05K2203/1316 , H05K2203/1327
Abstract: A system and method for providing a packaged electronics module having a dry film battery incorporated therein is disclosed. The packaged electronics module includes a first dielectric layer, at least one electronic component attached to or embedded in the first dielectric layer, a dry film battery formed on the first dielectric layer, and metal interconnects mechanically and electrically coupled to the at least one electronic component and the dry film battery to form electrical interconnections thereto. Electronic components in the form of a MEMS type sensor, semiconductor device and communications device may be included in the module along with the battery to provide a self-powered module capable of communicating with other like packaged electronics modules.
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公开(公告)号：US20170063326A1
公开(公告)日：2017-03-02
申请号：US14841314
申请日：2015-08-31
Applicant: GENERAL ELECTRIC COMPANY
Inventor： Christopher James Kapusta , Marco Francesco Aimi
CPC classification number: H03H9/02535 , G01L1/165 , G01L3/10 , H03H3/08 , H03H9/058 , H03H9/0595 , H03H9/10 , H03H9/1064 , H03H9/19 , H03H2003/0478
Abstract: In one embodiment, a bonded quartz wafer package includes a first quartz wafer including at least one quartz-based device, a second quartz wafer disposed above the first quartz wafer, and a liquid crystal polymer (LCP) bonding layer disposed in between the first and second quartz wafers that bonds the first and second quartz wafers together.
Abstract translation: 在一个实施例中，键合石英晶片封装包括第一石英晶片，其包括至少一个基于石英的器件，设置在第一石英晶片上方的第二石英晶片，以及液晶聚合物（LCP）接合层，其设置在第一和 将第一和第二石英晶片结合在一起的第二石英晶片。
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公开(公告)号：US20160155693A1
公开(公告)日：2016-06-02
申请号：US14556258
申请日：2014-12-01
Applicant: General Electric Company
Inventor： Scott Smith , Christopher James Kapusta , Glenn Alan Forman , Eric Patrick Davis
IPC: H01L23/498 , H01L23/00 , H01L21/288 , H01L25/065 , H01L21/48
CPC classification number: H01L23/49827 , H01L21/2885 , H01L21/486 , H01L22/12 , H01L22/14 , H01L22/22 , H01L23/49838 , H01L24/24 , H01L24/29 , H01L24/82 , H01L24/83 , H01L24/97 , H01L25/0655 , H01L2224/0401 , H01L2224/04042 , H01L2224/04105 , H01L2224/12105 , H01L2224/16227 , H01L2224/2919 , H01L2224/32225 , H01L2224/82031 , H01L2224/82039 , H01L2224/82047 , H01L2224/82106 , H01L2224/82138 , H01L2224/83129 , H01L2224/8314 , H01L2224/83192 , H01L2224/92144 , H01L2224/97 , H01L2225/1035 , H01L2225/1058 , H01L2924/01022 , H01L2924/01024 , H01L2924/01028 , H01L2924/01073 , H01L2924/01074 , H01L2924/01079 , H01L2924/14 , H01L2924/1433 , H01L2924/15724 , H01L2924/15738 , H01L2924/15747 , H01L2924/15763 , H01L2924/3025 , H01L2224/83 , H01L2224/82
Abstract: An electronic package and a method of making the same in provided. The electronic package includes a dielectric layer and a conformal masking layer disposed on at least a portion of the dielectric layer. The electronic package further includes a routing layer disposed on at least a portion of the masking layer and a micro-via disposed at least in part in the conformal masking layer and the routing layer. Further, at least a portion of the routing layer forms a conformal electrically conductive layer in at least a portion of the micro-via. Also, the conformal masking layer is configured to define a size of the micro-via. The electronic package further includes a semiconductor die operatively coupled to the micro-via.
Abstract translation: 一种电子封装及其制造方法。 电子封装包括介电层和设置在电介质层的至少一部分上的保形掩模层。 电子封装还包括设置在掩模层的至少一部分上的布线层和至少部分地设置在保形掩模层和布线层中的微通孔。 此外，路由层的至少一部分在微通孔的至少一部分中形成共形导电层。 此外，共形掩模层被配置为限定微通孔的尺寸。 电子封装还包括可操作地耦合到微通孔的半导体管芯。
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公开(公告)号：US20150099948A1
公开(公告)日：2015-04-09
申请号：US14045809
申请日：2013-10-04
Applicant: General Electric Company
Inventor： Christopher James Kapusta , Eric Patrick Davis , Jason Harris Karp
IPC: G01L1/04 , A61B5/1455
CPC classification number: A61B5/14552 , A61B2562/046 , A61B2562/12 , Y10T29/49004 , Y10T29/49126
Abstract: A flexible embedded sensor array includes a first substrate, an electrically conductive pad disposed on at least a portion of the first substrate, and a plurality of sensors disposed on at least a portion of electrically conductive pads. Further, the flexible embedded sensor array includes an electrically non-conductive adhesive material disposed in proximity to one or more of the plurality of sensors, a second substrate, and an electrical contact disposed between at least a portion of the sensor and at least a portion of the second substrate.
Abstract translation: 柔性嵌入式传感器阵列包括第一衬底，设置在第一衬底的至少一部分上的导电焊盘以及设置在导电焊盘的至少一部分上的多个传感器。 此外，柔性嵌入式传感器阵列包括设置在多个传感器中的一个或多个传感器附近的非导电粘合材料，第二基板和设置在传感器的至少一部分之间的电触头和至少一部分 的第二基板。
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公开(公告)号：US20240266270A1
公开(公告)日：2024-08-08
申请号：US18166192
申请日：2023-02-08
Applicant: General Electric Company
Inventor： Arun Virupaksha Gowda , Ljubisa D. Stevanovic , Christopher James Kapusta , Robert Dwayne Gossman , Risto Ilkka Sakari Tuominen
IPC: H01L23/498 , H01L21/48
CPC classification number: H01L23/49838 , H01L21/486 , H01L23/49861
Abstract: A semiconductor assembly includes a semiconductor device and a POL-RDL package coupled to said device. The device includes an upper surface, a gate pad and at least one source pad disposed on said upper surface. The POL-RDL package includes a dielectric layer having at least one source pad electrically coupled to said at least one source pad of said device and at least one contact pad disposed. At least one trace connection having a resistivity value electrically couples said at least one source pad of said POL-RDL package to said at least one contact pad.
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Patent Agency Ranking
公开(公告)号：US20230273160A1
公开(公告)日：2023-08-31
申请号：US18134788
申请日：2023-04-14
Applicant: General Electric Company
CPC classification number: G01N29/223 , G01K11/265 , G01N29/2443 , G01N29/2462 , G01D11/245
Abstract: A system includes a sensor comprising a sensor bonding layer disposed on a surface of the sensor, wherein the sensor bonding layer is a metallic alloy. An inlay includes a planar outer surface, wherein the inlay may be disposed on a curved surface of a structure. A structure bonding layer may be disposed on the planar outer surface of the inlay, wherein the structure bonding layer is a metallic alloy. The sensor bonding layer is coupled to the structure bonding layer via a metallic joint, and the sensor is configured to sense data of the structure through the metallic joint, the structure bonding layer, and the sensor bonding layer. The inlay comprises at least one of a modulus of elasticity, a shape, a thickness, and a size configured to reduce strain transmitted to the sensor.
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27.发明授权公开(公告)号：US11503704B2
公开(公告)日：2022-11-15
申请号：US16730435
申请日：2019-12-30
Applicant: General Electric Company
IPC: H05K1/02 , H05K1/03 , H05K1/09 , H05K1/11 , H05K1/14 , H05K1/16 , H05K1/18 , H05K3/10 , H05K3/32 , H05K3/36 , H05K3/42 , H05K3/46 , H01L21/02 , H01L21/48 , H01L21/50 , H01L21/56 , H01L23/00 , H01L23/12 , H01L23/13 , H01L23/16 , H01L23/31 , H01L23/48 , H01L23/52 , H01L23/58 , H01L23/66 , H01L23/485 , H01L23/498 , H01L23/538
Abstract: An electronics package is disclosed. The electronics package includes a first radio frequency (RF) substrate layer, a second RF substrate layer, and a plurality of conductive layers disposed adjacent to at least one of the first RF substrate layer and the second RF substrate layer and including an inner conductive layer disposed between and adjacent to both the first RF substrate layer and the second RF substrate layer. The inner conductive layer bonds the first RF substrate layer to the second RF substrate layer. The electronics package also includes a plurality of conductive interconnects extending through the first RF substrate layer and the second RF substrate layer and electrically coupled between at least two of the plurality of conductive layers.
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公开(公告)号：US20210325348A1
公开(公告)日：2021-10-21
申请号：US17362407
申请日：2021-06-29
Applicant: General Electric Company
Abstract: A system includes a sensor comprising a sensor bonding layer disposed on a surface of the sensor, wherein the sensor bonding layer is a metallic alloy. An inlay includes a planar outer surface, wherein the inlay may be disposed on a curved surface of a structure. A structure bonding layer may be disposed on the planar outer surface of the inlay, wherein the structure bonding layer is a metallic alloy. The sensor bonding layer is coupled to the structure bonding layer via a metallic joint, and the sensor is configured to sense data of the structure through the metallic joint, the structure bonding layer, and the sensor bonding layer. The inlay comprises at least one of a modulus of elasticity, a shape, a thickness, and a size configured to reduce strain transmitted to the sensor.
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公开(公告)号：US10892231B2
公开(公告)日：2021-01-12
申请号：US16667376
申请日：2019-10-29
Applicant: General Electric Company
Inventor： Christopher James Kapusta , Raymond Albert Fillion , Risto Ilkka Sakari Tuominen , Kaustubh Ravindra Nagarkar
IPC: H01L21/48 , H01L21/56 , H01L21/52 , H01L23/31 , H01L23/552 , H01L23/00 , H01L23/498 , H01L23/538
Abstract: An electronics package includes a support substrate, an electrical component having a first surface coupled to a first surface of the support substrate, and an insulating structure coupled to the first surface of the support substrate and sidewalls of the electrical component. The insulating structure has a sloped outer surface. A conductive layer encapsulates the electrical component and the sloped outer surface of the insulating structure. A first wiring layer is formed on a second surface of the support substrate. The first wiring layer is coupled to the conductive layer through at least one via in the support substrate.
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公开(公告)号：US10431509B2
公开(公告)日：2019-10-01
申请号：US14529311
申请日：2014-10-31
Applicant: General Electric Company
Inventor： Christopher James Kapusta , Marco Francesco Aimi
IPC: H01L23/552 , H01L23/10 , B81B7/00
Abstract: A non-magnetic hermetic package includes walls that surround an open cavity, with a generally planar non-magnetic and metallic seal ring disposed in a continuous loop around upper edges of the walls; a sensitive component that is bonded within the cavity; and a non-magnetic lid that is sealed to the seal ring to close the cavity by a metallic seal.
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