公开(公告)号：US20130214426A1

公开(公告)日：2013-08-22

申请号：US13665634

申请日：2012-10-31

Applicant: Broadcom Corporation

Inventor： Sam Ziqun Zhao ,  Rezaur Rahman Khan

IPC: H01L23/48

CPC classification number: H01L23/481 ,  H01L21/4857 ,  H01L23/14 ,  H01L23/145 ,  H01L23/147 ,  H01L23/49506 ,  H01L23/49575 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/5226 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/97 ,  H01L25/00 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/14183 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/17181 ,  H01L2224/30183 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/1515 ,  H01L2924/15153 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00

Abstract: The present application discloses various implementations of a semiconductor package including an organic substrate and one or more interposers having through-semiconductor vias (TSVs). Such a semiconductor package may include a contiguous organic substrate having a lower substrate segment including first and second pluralities of lower interconnect pads, the second plurality of lower interconnect pads being disposed in an opening of the lower substrate segment. The contiguous organic substrate may also include an upper substrate segment having an upper width and including first and second pluralities of upper interconnect pads. In addition, the semiconductor package may include at least one interposer having TSVs for electrically connecting the first and second pluralities of lower interconnect pads to the first and second pluralities of upper interconnect pads. The interposer has an interposer width less than the upper width of the upper substrate segment.

Abstract translation: 本申请公开了包括有机衬底和具有贯通半导体通孔（TSV）的一个或多个中介层的半导体封装的各种实施方式。 这种半导体封装可以包括具有包括第一和第二多个下部互连焊盘的下部衬底区段的连续有机衬底，第二多个下部互连焊盘设置在下部衬底段的开口中。 连续的有机衬底还可以包括具有上部宽度并包括第一和第二多个上部互连焊盘的上部衬底区段。 此外，半导体封装可以包括具有TSV的至少一个插入器，用于将第一和第二多个下部互连焊盘电连接到第一和第二多个上部互连焊盘。 插入器具有小于上基板段的上宽度的插入器宽度。

公开(公告)号：US20170301651A1

公开(公告)日：2017-10-19

申请号：US15144458

申请日：2016-05-02

Applicant: BROADCOM CORPORATION

Inventor： Sam Ziqun Zhao ,  Rezaur Rahman Khan

IPC: H01L25/065 ,  H01L21/768 ,  H01L23/31 ,  H01L21/56 ,  H01L23/48 ,  H01L23/00 ,  H01L25/00 ,  H01L23/367

CPC classification number: H01L25/0657 ,  H01L21/565 ,  H01L21/76885 ,  H01L23/3128 ,  H01L23/3675 ,  H01L23/481 ,  H01L24/11 ,  H01L24/13 ,  H01L24/19 ,  H01L24/96 ,  H01L25/03 ,  H01L25/50 ,  H01L2224/11334 ,  H01L2224/13014 ,  H01L2224/13016 ,  H01L2224/13022 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06548 ,  H01L2225/06568 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2924/01029

Abstract: A package such as a system in package (SiP) includes a first die disposed in a first mold layer and coupled to a first dielectric layer disposed above the first mold and a second die disposed in a second mold layer and coupled to a second dielectric layer disposed above the second die. A pillar is disposed through the second mold layer and is coupled to a first metal layer disposed above the first dielectric layer. The first metal layer is coupled to the first die, and the pillar is coupled to a second metal layer disposed above the second dielectric layer.

公开(公告)号：US20170110384A1

公开(公告)日：2017-04-20

申请号：US14928765

申请日：2015-10-30

Applicant: Broadcom Corporation

Inventor： Sam Ziqun Zhao ,  Rezaur Rahman Khan

IPC: H01L23/367

CPC classification number: H01L23/367 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L24/83 ,  H01L2224/16227 ,  H01L2224/291 ,  H01L2224/29113 ,  H01L2224/2919 ,  H01L2224/29191 ,  H01L2224/29193 ,  H01L2224/29194 ,  H01L2224/29291 ,  H01L2224/29299 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/83101 ,  H01L2224/83385 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/16251 ,  H01L2924/1659 ,  H01L2924/3511 ,  H01L2924/0782 ,  H01L2924/0665 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/01006 ,  H01L2924/013 ,  H01L2924/014 ,  H01L2924/0715

Abstract: In embodiments described herein, an integrated circuit (IC) package is provided. The IC package may include a substrate, an IC die, and a heat spreader. The IC die may have opposing first and second surfaces, where the first surface of the IC die is coupled to a surface of the substrate. The heat spreader may have a surface coupled to the second surface of the IC die by a thermal interface (TI) material. The surface of the heat spreader may have a micro-recess which may include a micro-channel or a micro-dent to direct a flow of TI material towards or away from a predetermined area of the second surface of the IC die based on temperatures of the substrate, the IC die, and/or the heat spreader.

公开(公告)号：US09024436B2

公开(公告)日：2015-05-05

申请号：US13921594

申请日：2013-06-19

Applicant: Broadcom Corporation

Inventor： Sam Ziqun Zhao ,  Arpit Mittal ,  Rezaur Rahman Khan

IPC: H01L23/34 ,  H05K1/02 ,  H01L23/373 ,  H01L21/02 ,  H01L29/06 ,  H01L51/00

CPC classification number: H01L23/373 ,  B82Y10/00 ,  B82Y99/00 ,  F28F21/02 ,  F28F21/081 ,  H01L21/02112 ,  H01L21/4882 ,  H01L23/3735 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L29/0669 ,  H01L29/0676 ,  H01L51/0048 ,  H01L2223/64 ,  H01L2224/16225 ,  H01L2224/2908 ,  H01L2224/29193 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/83192 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/16251 ,  H01L2924/167 ,  H01L2924/351 ,  H05K1/0203 ,  Y10S977/742 ,  H01L2924/00

Abstract: In an embodiment, a thermal interface material (TIM) is provided. The TIM includes first and a second layers of a first transition metal, and a third layer including a plurality of carbon nanotubes supported in a flexible polymer matrix and a second transition metal coupled to sidewalls of carbon nanotubes. The first and second metal layers are in contact with first and second ends of carbon nanotube. The TIM further includes fourth and fifth layers of an alloy material coupled to the first and second metal layers, respectively. The carbon nanotube based TIM including the layers with transition metal allow improved heat transfer from an integrated circuit die to a heat spreader.

Abstract translation: 在一个实施例中，提供了热界面材料（TIM）。 TIM包括第一和第二层第一过渡金属，第三层包括支撑在柔性聚合物基体中的多个碳纳米管和耦合到碳纳米管的侧壁的第二过渡金属。 第一和第二金属层与碳纳米管的第一和第二端接触。 TIM还包括分别耦合到第一和第二金属层的合金材料的第四层和第五层。 包括具有过渡金属的层的基于碳纳米管的TIM允许改进从集成电路管芯到散热器的热传递。

公开(公告)号：US08829655B2

公开(公告)日：2014-09-09

申请号：US14079356

申请日：2013-11-13

Applicant: Broadcom Corporation

Inventor： Sam Ziqun Zhao ,  Rezaur Rahman Khan

IPC: H01L29/40 ,  H01L23/02 ,  H01L23/48 ,  H01L23/52 ,  H01L21/48 ,  H01L23/522 ,  H01L23/538 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/481 ,  H01L21/4857 ,  H01L23/14 ,  H01L23/145 ,  H01L23/147 ,  H01L23/49506 ,  H01L23/49575 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/5226 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/97 ,  H01L25/00 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/14183 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/17181 ,  H01L2224/30183 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/1515 ,  H01L2924/15153 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00

Abstract: The present application discloses various implementations of a semiconductor package including an organic substrate and one or more interposers having through-semiconductor vias (TSVs). Such a semiconductor package may include a contiguous organic substrate having a lower substrate segment including first and second pluralities of lower interconnect pads, the second plurality of lower interconnect pads being disposed in an opening of the lower substrate segment. The contiguous organic substrate may also include an upper substrate segment having an upper width and including first and second pluralities of upper interconnect pads. In addition, the semiconductor package may include at least one interposer having TSVs for electrically connecting the first and second pluralities of lower interconnect pads to the first and second pluralities of upper interconnect pads. The interposer has an interposer width less than the upper width of the upper substrate segment.

Abstract translation: 本申请公开了包括有机衬底和具有贯通半导体通孔（TSV）的一个或多个中介层的半导体封装的各种实施方式。 这种半导体封装可以包括具有包括第一和第二多个下部互连焊盘的下部衬底区段的连续有机衬底，第二多个下部互连焊盘设置在下部衬底段的开口中。 连续的有机衬底还可以包括具有上部宽度并包括第一和第二多个上部互连焊盘的上部衬底区段。 此外，半导体封装可以包括具有TSV的至少一个插入器，用于将第一和第二多个下部互连焊盘电连接到第一和第二多个上部互连焊盘。 插入器具有小于上基板段的上宽度的插入器宽度。

公开(公告)号：US08829654B2

公开(公告)日：2014-09-09

申请号：US14078799

申请日：2013-11-13

Applicant: Broadcom Corporation

Inventor： Sam Ziqun Zhao ,  Rezaur Rahman Khan

IPC: H01L29/40 ,  H01L23/02 ,  H01L23/48 ,  H01L23/52 ,  H01L21/48 ,  H01L23/522 ,  H01L23/538 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/481 ,  H01L21/4857 ,  H01L23/14 ,  H01L23/145 ,  H01L23/147 ,  H01L23/49506 ,  H01L23/49575 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/5226 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/97 ,  H01L25/00 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/14183 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/17181 ,  H01L2224/30183 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/1515 ,  H01L2924/15153 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00

Abstract: The present application discloses various implementations of a semiconductor package including an organic substrate and one or more interposers having through-semiconductor vias (TSVs). Such a semiconductor package may include a contiguous organic substrate having a lower substrate segment including first and second pluralities of lower interconnect pads, the second plurality of lower interconnect pads being disposed in an opening of the lower substrate segment. The contiguous organic substrate may also include an upper substrate segment having an upper width and including first and second pluralities of upper interconnect pads. In addition, the semiconductor package may include at least one interposer having TSVs for electrically connecting the first and second pluralities of lower interconnect pads to the first and second pluralities of upper interconnect pads. The interposer has an interposer width less than the upper width of the upper substrate segment.

Abstract translation: 本申请公开了包括有机衬底和具有贯通半导体通孔（TSV）的一个或多个中介层的半导体封装的各种实施方式。 这种半导体封装可以包括具有包括第一和第二多个下部互连焊盘的下部衬底区段的连续有机衬底，第二多个下部互连焊盘设置在下部衬底段的开口中。 连续的有机衬底还可以包括具有上部宽度并包括第一和第二多个上部互连焊盘的上部衬底区段。 此外，半导体封装可以包括具有TSV的至少一个插入器，用于将第一和第二多个下部互连焊盘电连接到第一和第二多个上部互连焊盘。 插入器具有小于上基板段的上宽度的插入器宽度。

公开(公告)号：US20140061946A1

公开(公告)日：2014-03-06

申请号：US14079571

申请日：2013-11-13

Applicant: Broadcom Corporation

Inventor： Sam Ziqun Zhao ,  Rezaur Rahman Khan

IPC: H01L23/14 ,  H01L25/00

CPC classification number: H01L23/481 ,  H01L21/4857 ,  H01L23/14 ,  H01L23/145 ,  H01L23/147 ,  H01L23/49506 ,  H01L23/49575 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/5226 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/97 ,  H01L25/00 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/14183 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/17181 ,  H01L2224/30183 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/1515 ,  H01L2924/15153 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00

Abstract: The present application discloses various implementations of a semiconductor package including an organic substrate and one or more interposers having through-semiconductor vias (TSVs). Such a semiconductor package may include a contiguous organic substrate having a lower substrate segment including first and second pluralities of lower interconnect pads, the second plurality of lower interconnect pads being disposed in an opening of the lower substrate segment. The contiguous organic substrate may also include an upper substrate segment having an upper width and including first and second pluralities of upper interconnect pads. In addition, the semiconductor package may include at least one interposer having TSVs for electrically connecting the first and second pluralities of lower interconnect pads to the first and second pluralities of upper interconnect pads. The interposer has an interposer width less than the upper width of the upper substrate segment.

Abstract translation: 本申请公开了包括有机衬底和具有贯通半导体通孔（TSV）的一个或多个中介层的半导体封装的各种实施方式。 这种半导体封装可以包括具有包括第一和第二多个下部互连焊盘的下部衬底区段的连续有机衬底，第二多个下部互连焊盘设置在下部衬底段的开口中。 连续的有机衬底还可以包括具有上部宽度并包括第一和第二多个上部互连焊盘的上部衬底区段。 此外，半导体封装可以包括具有TSV的至少一个插入器，用于将第一和第二多个下部互连焊盘电连接到第一和第二多个上部互连焊盘。 插入器具有小于上基板段的上宽度的插入器宽度。

公开(公告)号：US08664772B2

公开(公告)日：2014-03-04

申请号：US14051817

申请日：2013-10-11

Applicant: Broadcom Corporation

Inventor： Rezaur Rahman Khan ,  Sam Ziqun Zhao

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/02

CPC classification number: H01L23/481 ,  H01L23/12 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L25/105 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/17181 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00

Abstract: An interface substrate is disclosed which includes an interposer having through-semiconductor vias. An upper and a lower organic substrate are further built around the interposer. The disclosed interface substrate enables the continued use of low cost and widely deployed organic substrates for semiconductor packages while providing several advantages. The separation of the organic substrate into upper and lower substrates enables the cost effective matching of fabrication equipment. By providing an opening in one of the organic substrates, one or more semiconductor dies may be attached to exposed interconnect pads coupled to through-semiconductor vias of the interposer, enabling the use of flip chips with high-density microbump arrays and the accommodation of dies with varied bump pitches. By providing the opening specifically in the upper organic substrate, a package-on-package structure with optimized height may also be provided.

Abstract translation: 公开了一种界面衬底，其包括具有贯通半导体通孔的插入件。 进一步围绕插入件构建上部和下部有机衬底。 所公开的接口衬底能够持续使用低成本且广泛部署的用于半导体封装的有机衬底，同时提供若干优点。 将有机基底分离成上下基板能够实现制造设备的成本有效匹配。 通过在一个有机衬底中设置一个开口，一个或多个半导体管芯可以附着到与插入器的通孔半导体连接的暴露的互连焊盘上，使得能够使用具有高密度微型阵列的倒装芯片和模具 具有不同的凸起间距。 通过在上部有机衬底中提供开口，还可以提供具有优化的高度的封装封装结构。

公开(公告)号：US20170365565A1

公开(公告)日：2017-12-21

申请号：US15198991

申请日：2016-06-30

Applicant: Broadcom Corporation

Inventor： Sam Ziqun ZHAO ,  Rezaur Rahman Khan

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L21/60

CPC classification number: H01L21/4853 ,  H01L21/561 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3128 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/82 ,  H01L24/96 ,  H01L2021/60135 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/24011 ,  H01L2224/24101 ,  H01L2224/24137 ,  H01L2224/25171 ,  H01L2224/73267 ,  H01L2224/96 ,  H01L2924/18161 ,  H01L2224/82 ,  H01L2224/11 ,  H01L2924/014

Abstract: An integrated circuit (IC) package is disclosed that contains high density interconnects to connect multiple dies. The IC package includes an encapsulated layer, a first dielectric layer, and a second dielectric layer. The encapsulated layer forms the base of the IC package and includes the multiple dies. The first dielectric layer positioned between the encapsulated layer and the second layer. The first dielectric layer includes vias to connect to the input/ouput pads of active surfaces of the multiple dies. The second dielectric layer includes interconnect layers where at least one of the interconnect layers forms an electrical path to connect at least two of the multiple dies together. According to embodiments of the present disclosure, the IC package enables a high manufacturing yield due to large tolerances allowed for selection of dies. Embodiments of the present disclosure also increase an amount of input/output interconnection between multiple dies in the IC package. Embodiments of the present disclosure further enable lower manufacturing costs because of the use of mature reconstituted dies and redistribution layer technologies and the lack of a need for an interposer to connect multiple dies.

公开(公告)号：US09693461B2

公开(公告)日：2017-06-27

申请号：US14684256

申请日：2015-04-10

Applicant: BROADCOM CORPORATION

Inventor： Sam Ziqun Zhao ,  Edward Law ,  Sampath Komarapalayam Karikalan ,  Neal Andrew Kistler ,  Rezaur Rahman Khan ,  Pieter Vorenkamp

IPC: H01F5/00 ,  H05K1/18 ,  H01F17/00 ,  H01F41/04 ,  H01F27/28 ,  H01F17/04 ,  H01F38/14

CPC classification number: H05K1/181 ,  H01F17/0013 ,  H01F17/045 ,  H01F38/14 ,  H01F41/046 ,  H01F2017/0053 ,  H01F2017/0066 ,  H01F2027/2809 ,  H01L2224/16225

Abstract: A 3-dimensional (3-D) magnetic core device includes a substrate, a first magnetic shell formed on the substrate, and a first group of conductive traces embedded in a first insulator layer formed on the first magnetic shell. A magnetic core plane is formed on the first insulator layer, and a second group of conductive traces are embedded in a second insulator layer formed on the magnetic core plane. A second magnetic shell is formed on the second insulator layer, and the first and second group of conductive traces are conductively coupled by using conductive vias.