公开(公告)号：US20240428870A1

公开(公告)日：2024-12-26

申请号：US18744919

申请日：2024-06-17

Applicant: Kioxia Corporation

Inventor： Hayato KONNO ,  Makoto MIAKASHI

IPC: G11C16/34 ,  G11C16/16

Abstract: A memory includes a plurality of planes, a controller, and a source line. The controller is configured to erase data of each memory cell in an erase target block selected in each of the planes, by executing an erase sequence that repeats a plurality of loops, each of the loops including a set of an erase operation that erases the data of each memory cell in the erase target block and an erase verification operation that checks whether the data is erased. For each erase target block, the controller is configured to detect whether there is a current leak from the source line, determine validity of the erase sequence based on a detection result, and stop execution of the erase sequence for the erase target blocks that are determined not to be valid.

公开(公告)号：US20240428861A1

公开(公告)日：2024-12-26

申请号：US18514704

申请日：2023-11-20

Applicant: SK hynix Inc.

Inventor： Suk Hwan CHOI ,  Dong Hun KWAK ,  Se Chun PARK

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/16 ,  G11C16/34

Abstract: An operating method of a memory device may include performing a pre-program operation on selection transistors that are included in strings, wherein each of the strings comprises a first source selection transistor, a second source selection transistor, a plurality of memory cells, and a drain selection transistor that are sequentially coupled, and performing an erase operation and a fine program operation on at least one of the selection transistors.

公开(公告)号：US20240420774A1

公开(公告)日：2024-12-19

申请号：US18815433

申请日：2024-08-26

Applicant: KIOXIA CORPORATION

Inventor： Jun NAKAI ,  Noboru SHIBATA

IPC: G11C16/16 ,  G11C16/14 ,  G11C16/26 ,  G11C16/34

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array and a control unit. The memory cell array includes a plurality of memory cells arranged in a matrix. The control unit erases data of the memory cells. The control unit interrupts the erase operation of the memory cells and holds an erase condition before the interrupt in accordance with a first command during the erase operation, and resumes the erase operation based on the held erase condition in accordance with a second command.

公开(公告)号：US20240395332A1

公开(公告)日：2024-11-28

申请号：US18359829

申请日：2023-07-26

Applicant: Western Digital Technologies, Inc.

Inventor： Ming Wang ,  Liang Li

IPC: G11C16/16 ,  G11C16/04 ,  G11C16/08 ,  G11C16/24

Abstract: A non-volatile memory includes non-volatile memory cells divided into blocks, bit lines connected to the blocks, and a source line connected to the blocks. Each block includes multiple sub-blocks. Each sub-block includes multiple source side Gate Induced Drain Leakage (“GIDL”) generation transistors that are closer to the source line than the bit lines. GIDL generation transistors for each sub-block can be controlled separately from GIDL generation transistors for other sub-blocks of the same sub-block so that sub-blocks can be separately and independently erased and/or GIDL can be used to inhibit unselected sub-blocks from bring disturbed during programming.

公开(公告)号：US12153820B2

公开(公告)日：2024-11-26

申请号：US17206147

申请日：2021-03-19

Applicant: Silicon Motion, Inc.

Inventor： Tzu-Yi Yang

IPC: G06F3/06 ,  G11C11/56 ,  G11C16/16 ,  G11C16/34

Abstract: A method of performing a wear-leveling operation in a flash memory includes: determining a block age for each of a plurality of blocks in the flash memory according to a number of erase operations that have been performed on the flash memory after the block is erased; selecting one or more candidate source blocks from the plurality of blocks by comparing block ages of the plurality of blocks with an age limit; determining a source block from the one or more candidate source blocks according to erase counts or block ages of the one or more candidate source blocks; and performing the wear-leveling operation on the source block.

公开(公告)号：US20240379175A1

公开(公告)日：2024-11-14

申请号：US18360075

申请日：2023-07-27

Applicant: Western Digital Technologies, Inc.

Inventor： Yi Song ,  Jiahui Yuan ,  Jiacen Guo ,  Xiang Yang

IPC: G11C16/34 ,  G11C16/16

Abstract: Technology is disclosed herein for a storage system that mitigates erase saturation when erasing memory cells. If erase does not pass after a number of erase loops, the storage system applies a program pulse to memory cells on faster to erase NAND strings. However, memory cells on slower to erase NAND strings are inhibited from programming. The program pulse increases the Vt of memory cells on the faster to erase NAND strings. Then, another erase loop is performed. The process may continue with additional loops, with each loop programming the memory cells on the faster to erase NAND strings followed by an erase pulse to all NAND strings and erase verify. Over-erase of the memory cells on the faster to erase NAND strings is therefore prevented. Moreover, slower to erase NAND strings that may otherwise be a bottleneck do not prevent successful completion of the erase.

公开(公告)号：US20240363176A1

公开(公告)日：2024-10-31

申请号：US18638788

申请日：2024-04-18

Applicant: Kioxia Corporation

Inventor： Viktoria Diana SCHLYKOW ,  Reika TANAKA

IPC: G11C16/34 ,  G11C11/22 ,  G11C16/04 ,  G11C16/10 ,  G11C16/16 ,  H10B43/27 ,  H10B51/20

CPC classification number: G11C16/3404 ,  G11C11/223 ,  G11C11/2275 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/16 ,  H10B43/27 ,  H10B51/20

Abstract: A semiconductor memory device of embodiments includes a semiconductor layer, a gate electrode layer, memory cells each including a gate insulating layer containing Si, O, and N, and a control circuit. The control circuit performs a write operation and an erase operation on the memory cells. The control circuit determine whether or not the number of times of execution of the erase operation on the memory cells has reached a predetermined number of times. When the number has reached the predetermined number of times, the control circuit perform first processing and second processing on the memory cells. The first processing applies a voltage with the same polarity as that in the write operation to the gate electrode layer with a pulse width larger than that in the write operation. The second processing applies a voltage with a polarity opposite to that in the write operation to the gate electrode layer.

公开(公告)号：US20240363170A1

公开(公告)日：2024-10-31

申请号：US18363518

申请日：2023-08-01

Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.,

Inventor： Naoto NORIZUKI ,  Hiroki YABE

IPC: G11C16/16 ,  G11C16/04 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18 ,  H10B41/27 ,  H10B43/27 ,  H10B80/00

CPC classification number: G11C16/16 ,  G11C16/0483 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H10B41/27 ,  H10B43/27 ,  H10B80/00 ,  H01L2224/08145 ,  H01L2224/80006 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A semiconductor device includes a plurality of memory blocks and a bit-line-bias block. A source-drain erase bias voltage is applied between a source line and a bit lines through the bit-line-bias block during an erase operation.

公开(公告)号：US12131785B2

公开(公告)日：2024-10-29

申请号：US17829837

申请日：2022-06-01

Applicant: Intel NDTM US LLC

Inventor： Chao Zhang ,  Krishna Parat ,  Richard Fastow ,  Ricardo Basco ,  Xin Sun ,  Heonwook Kim ,  Zhan Liu

IPC: G11C16/08 ,  G11C7/04 ,  G11C16/16 ,  G11C16/24 ,  G11C16/26 ,  G11C16/34

CPC classification number: G11C16/16 ,  G11C7/04 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26 ,  G11C16/349

Abstract: Systems, apparatuses and methods may provide for technology that biases a word line of a block in NAND memory to a first voltage level, biases a source-side select gate and a drain-side select gate of the block to a second voltage level, and issues a discharge erase pulse to bitlines and a source of the block, wherein the discharge erase pulse is issued at a third voltage level, wherein the third voltage level is greater than the first voltage level and the second voltage level, and wherein the third voltage level is less than a fourth voltage level of a standard erase pulse. In one example, the discharge erase pulse injects holes into pillars of the block and bypasses an erase of cells in the pillars of the block.

公开(公告)号：US12100459B2

公开(公告)日：2024-09-24

申请号：US18333661

申请日：2023-06-13

Applicant: KIOXIA CORPORATION

Inventor： Shinya Okuno ,  Shigeki Nagasaka ,  Toshiyuki Kouchi

IPC: G11C16/04 ,  G06F5/06 ,  G06F13/16 ,  G11C7/02 ,  G11C7/10 ,  G11C16/10 ,  G11C16/12 ,  G11C16/16 ,  G11C16/26 ,  G11C16/32

CPC classification number: G11C16/32 ,  G06F5/06 ,  G06F13/1673 ,  G11C7/02 ,  G11C7/1012 ,  G11C7/1039 ,  G11C7/106 ,  G11C7/1066 ,  G11C16/10 ,  G11C16/12 ,  G11C16/16 ,  G11C16/26 ,  G06F2205/067 ,  G11C16/0483 ,  G11C2207/108 ,  G11C2207/2281 ,  Y02D10/00

Abstract: A semiconductor device includes a memory circuit, a first FIFO, a second FIFO and an input/output circuit. The memory circuit outputs data. The first FIFO receives data from the memory circuit and outputs data synchronously with a first clock signal. The second FIFO receives data output from the first FIFO and outputs data synchronously with the first clock signal. The input/output circuit outputs data output from the second FIFO. The second FIFO is disposed in the vicinity of the input/output circuit than the first FIFO.