公开(公告)号：US10141315B2

公开(公告)日：2018-11-27

申请号：US15618442

申请日：2017-06-09

Applicant: Zeno Semiconductor, Inc.

Inventor： Yuniarto Widjaja ,  Zvi Or-Bach

IPC: G11C7/00 ,  H01L27/108 ,  G11C11/404 ,  H01L29/78 ,  H01L29/772 ,  G11C7/22 ,  G11C11/4074 ,  G11C11/4094 ,  H01L23/528 ,  H01L29/10 ,  G11C11/4096 ,  G11C14/00 ,  H01L29/66 ,  H01L29/788 ,  G11C11/39 ,  G11C11/04 ,  G11C11/402

Abstract: An IC may include an array of memory cells formed in a semiconductor, including memory cells arranged in rows and columns, each memory cell may include a floating body region defining at least a portion of a surface of the memory cell, the floating body region having a first conductivity type; a buried region located within the memory cell and located adjacent to the floating body region, wherein the buried region has a second conductivity type, wherein the floating body region is bounded on a first side by a first insulating region having a first thickness and on a second side by a second insulating region having a second thickness, and a gate region above the floating body region and the second insulating region and is insulated from the floating body region by an insulating layer; and control circuitry configured to provide electrical signals to said buried region.

公开(公告)号：US10032500B2

公开(公告)日：2018-07-24

申请号：US15289023

申请日：2016-10-07

Applicant: Kilopass Technology, Inc.

Inventor： Adrian E. Ong ,  Charles Cheng

IPC: G11C11/34 ,  G11C11/39 ,  G11C15/04

Abstract: Methods and systems are described herein for determining if bit cell read or write rates require a refresh of the accessed or neighboring bit cells. The refresh of VLT memory bit cells that undergo a high frequency of page address read operations and write operations helps to maintain integrity of data stored in the VLT memory bit cells. The methods and systems determine, during each RAS cycle, if a rate of Page Address read operations or write operations exceeds a maximum rate across an interval, and conditionally cause a refresh operation if the rate exceeds the maximum rate. The methods and systems output a write back signal to cause a refresh of the associated VLT memory bit cells to prevent corruption of data stored in the associated VLT memory bit cells.

公开(公告)号：US10020308B2

公开(公告)日：2018-07-10

申请号：US15349978

申请日：2016-11-11

Applicant: Kilopass Technology, Inc.

Inventor： Harry Luan ,  Bruce L. Bateman ,  Valery Axelrad ,  Charlie Cheng

IPC: H01L29/66 ,  H01L27/102 ,  H01L27/105 ,  H01L29/423 ,  H01L29/74 ,  G11C11/39 ,  H01L27/08 ,  H01L27/108 ,  H01L27/11

CPC classification number: H01L27/1027 ,  G11C11/39 ,  H01L27/0817 ,  H01L27/1023 ,  H01L27/1052 ,  H01L27/10805 ,  H01L27/11 ,  H01L29/42308 ,  H01L29/74

Abstract: A vertical thyristor memory array including: a vertical thyristor memory cell, the vertical thyristor memory cell including: a p+ anode; an n-base located below the p+ anode; a p-base located below the n-base; a n+ cathode located below the p-base; an isolation trench located around the vertical thyristor memory cell; an assist gate located in the isolation trench adjacent the n-base wherein an entire vertical height of the assist gate is positioned within an entire vertical height of the n-base.

公开(公告)号：US20170330623A1

公开(公告)日：2017-11-16

申请号：US15185388

申请日：2016-06-17

Applicant: Korea University Research and Business Foundation

Inventor： Sangsig Kim ,  Youngin Jeon ,  Minsuk Kim ,  Doohyeok Lim

IPC: G11C14/00 ,  H01L27/102 ,  H01L27/08 ,  G11C11/56 ,  H01L27/108 ,  G11C11/39

CPC classification number: G11C14/0018 ,  G11C11/39 ,  G11C11/404 ,  G11C11/5628 ,  G11C11/5671 ,  H01L27/0817 ,  H01L27/1027 ,  H01L27/108 ,  H01L27/10844 ,  H01L29/513 ,  H01L29/7391

Abstract: A memory device, an operating method of the memory device, and a fabricating method of the memory device are provided. A memory device includes: a semiconductor column extending vertically on a substrate and including a source region of a first conductivity type, an intrinsic region, and a drain region of a second conductivity type; a first gate electrode disposed adjacent to the drain region to cover the intrinsic region; a second gate electrode spaced apart from the first gate electrode and disposed adjacent to the source region to cover the intrinsic region; a first gate electrode disposed between the first gate electrode and the intrinsic region; and a second gate insulating layer disposed between the second gate electrode and the intrinsic region.

公开(公告)号：US09461156B2

公开(公告)日：2016-10-04

申请号：US14316806

申请日：2014-06-27

Applicant: Powerchip Technology Corporation

Inventor： Chen-Hao Huang ,  Chan-Ching Lin ,  Hann-Ping Hwang ,  Chun-Cheng Chen ,  Tzung-Bin Huang

IPC: H01L29/66 ,  H01L29/74 ,  G11C11/39 ,  H01L27/22 ,  H01L29/747 ,  H01L43/08

CPC classification number: H01L29/7404 ,  G11C11/39 ,  H01L27/226 ,  H01L29/747 ,  H01L43/08

Abstract: This invention provides a memory structure and an operation method thereof. The memory structure includes a triode for alternating current (TRIAC) and a memory cell. The memory cell is electrically connected to the TRIAC.

Abstract translation: 本发明提供一种存储器结构及其操作方法。 存储器结构包括用于交流的三极管（TRIAC）和存储器单元。 存储单元电连接到TRIAC。

公开(公告)号：US20160093369A1

公开(公告)日：2016-03-31

申请号：US14740209

申请日：2015-06-15

Applicant: Kilopass Technology, Inc.

Inventor： Harry Luan ,  Bruce L. Bateman ,  Valery Axelrad ,  Charlie Cheng ,  Christophe J. Chevallier

IPC: G11C11/419 ,  H01L27/11 ,  G11C11/418 ,  G11C11/39

CPC classification number: G11C11/39 ,  G11C5/14 ,  G11C11/34 ,  G11C11/4113 ,  G11C11/416 ,  G11C11/418 ,  G11C11/419 ,  H01L21/8249 ,  H01L27/0623 ,  H01L27/0821 ,  H01L27/0826 ,  H01L27/1027 ,  H01L27/11 ,  H01L27/1104

Abstract: A two-transistor memory cell based upon a thyristor for an SRAM integrated circuit is described together with methods of operation. The memory cell can be implemented in different combinations of MOS and bipolar select transistors, or without select transistors, with thyristors in a semiconductor substrate with shallow trench isolation. Standard CMOS process technology can be used to manufacture the SRAM.

Abstract translation: 基于用于SRAM集成电路的晶闸管的双晶体管存储单元与操作方法一起被描述。 存储器单元可以在具有浅沟槽隔离的半导体衬底中的晶闸管的MOS和双极选择晶体管的不同组合中实现，或者不具有选择晶体管。 标准CMOS工艺技术可用于制造SRAM。

公开(公告)号：US20160093356A1

公开(公告)日：2016-03-31

申请号：US14841521

申请日：2015-08-31

Applicant: Kilopass Technology, Inc.

Inventor： Harry Luan ,  Bruce L. Bateman ,  Valery Axelrad ,  Charlie Cheng

IPC: G11C11/39

CPC classification number: G11C11/39 ,  H01L27/1027 ,  H01L29/74 ,  H01L29/749

Abstract: A volatile memory array using vertical thyristors is disclosed together with methods of operating the array to read data from and write data to the array.

Abstract translation: 公开了使用垂直晶闸管的易失性存储器阵列以及操作阵列以从阵列读取数据并将数据写入阵列的方法。

公开(公告)号：US20160078917A1

公开(公告)日：2016-03-17

申请号：US14948097

申请日：2015-11-20

Applicant: Micron Technology, Inc.

Inventor： Farid Nemati ,  Scott T. Robins ,  Rajesh N. Gupta

IPC: G11C11/39

CPC classification number: G11C11/39 ,  H01L21/28008 ,  H01L21/30604 ,  H01L21/76224 ,  H01L27/0817 ,  H01L27/1027 ,  H01L29/7455 ,  H01L29/749

Abstract: Some embodiments include thyristors having first and second electrode regions, first and second base regions, and material having a bandgap of at least 1.2 eV in at least one of the regions. The first base region is between the first electrode region and the second base region, and the second base region is between the second electrode region and the first base region. The first base region interfaces with the first electrode region at a first junction, and interfaces with the second base region at a second junction. The second base region interfaces with the second electrode region at a third junction. A gate is along the first base region, and in some embodiments does not overlap either of the first and second junctions. Some embodiments include methods of programming thyristors, and some embodiments include methods of forming thyristors.

Abstract translation: 一些实施例包括具有第一和第二电极区域，第一和第二基极区域以及在至少一个区域中具有至少1.2eV的带隙的材料的晶闸管。 第一基极区域在第一电极区域和第二基极区域之间，第二基极区域在第二电极区域和第一基极区域之间。 第一基区在第一结处与第一电极区相接，并且在第二结处与第二基区交界。 第二基极区域在第三结区与第二电极区域相接合。 栅极沿着第一基极区域，并且在一些实施例中不与第一和第二结点重叠。 一些实施例包括编程晶闸管的方法，并且一些实施例包括形成晶闸管的方法。

公开(公告)号：US09246089B2

公开(公告)日：2016-01-26

申请号：US14145614

申请日：2013-12-31

Applicant: SanDisk 3D LLC

Inventor： Scott Brad Herner ,  Andrew Walker

IPC: H01L29/00 ,  H01L45/00 ,  G11C5/02 ,  G11C11/39 ,  G11C17/06 ,  G11C17/16 ,  H01L27/102

CPC classification number: H01L45/1233 ,  G11C5/02 ,  G11C11/39 ,  G11C17/06 ,  G11C17/16 ,  G11C2213/71 ,  G11C2213/77 ,  H01L27/1021

Abstract: A memory cell according to the present invention comprises a bottom conductor, a doped semiconductor pillar, and a top conductor. The memory cell does not include a dielectric rupture antifuse separating the doped semiconductor pillar from either conductor, or within the semiconductor pillar. The memory cell is formed in a high-impedance state, in which little or no current flows between the conductors on application of a read voltage. Application of a programming voltage programs the cell, converting the memory cell from its initial high-impedance state to a low-impedance state. A monolithic three dimensional memory array of such cells can be formed, comprising multiple memory levels, the levels monolithically formed above one another.

Abstract translation: 根据本发明的存储器单元包括底部导体，掺杂半导体柱和顶部导体。 存储单元不包括将掺杂半导体柱与任一导体或半导体柱分离的介电破裂反熔丝。 存储单元形成为在施加读取电压时在导体之间很少或没有电流流过的高阻抗状态。 应用编程电压对单元进行编程，将存储单元从其初始高阻抗状态转换为低阻抗状态。 可以形成这样的单元的单片三维存储器阵列，其包括多个存储器级，彼此之间单独形成的电平。

公开(公告)号：US08587996B2

公开(公告)日：2013-11-19

申请号：US12843212

申请日：2010-07-26

Applicant: Yogesh Luthra

Inventor： Yogesh Luthra

IPC: G11C11/39 ,  G11C11/35 ,  G11C11/40

CPC classification number: G11C5/02 ,  G11C5/06 ,  G11C7/00 ,  G11C11/402 ,  G11C16/26 ,  H01L27/1023 ,  H01L27/10802 ,  H01L29/73 ,  H01L29/7841

Abstract: Techniques for providing a direct injection semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method for biasing a direct injection semiconductor memory device including the steps of applying a first non-negative voltage potential to a first region via a bit line and applying a second non-negative voltage potential to a second region via a source line. The method may also include applying a third voltage potential to a word line, wherein the word line may be spaced apart from and capacitively to a body region that may be electrically floating and disposed between the first region and the second region. The method may further include applying a fourth positive voltage potential to a third region via a carrier injection line, wherein the third region may be disposed below at least one of the first region, the body region, and the second region.

Abstract translation: 公开了提供直接注入半导体存储器件的技术。 在一个特定的示例性实施例中，这些技术可以被实现为用于偏置直接注入半导体存储器件的方法，包括以下步骤：通过位线将第一非负电压电位施加到第一区域，并施加第二非负电压 通过源线向第二个区域提供电位。 该方法还可以包括将第三电压电位施加到字线，其中字线可以与可以电浮动并且布置在第一区域和第二区域之间的体区间隔开并且电容化。 该方法可以进一步包括经由载体注入管线将第四正电压电位施加到第三区域，其中第三区域可以设置在第一区域，体区域和第二区域中的至少一个之下。