公开(公告)号：US20230273823A1

公开(公告)日：2023-08-31

申请号：US18311686

申请日：2023-05-03

申请人： Marvell Asia Pte, Ltd.

发明人： Nathan Chrisman

IPC分类号： G06F9/50 ,  G06F12/0893 ,  G06F9/448 ,  G06F12/02 ,  G06F9/54 ,  G06F9/38 ,  G06F11/10 ,  G06F5/06 ,  G06F13/16

CPC分类号： G06F9/5016 ,  G06F12/0893 ,  G06F9/4488 ,  G06F12/0253 ,  G06F9/546 ,  G06F9/3818 ,  G06F11/1004 ,  G06F5/065 ,  G06F9/3877 ,  G06F9/548 ,  G06F13/1673 ,  G06F2213/0026

摘要： A hardware client and corresponding method employ an object-oriented memory device. The hardware client generates an object-oriented message associated with an object of an object class. The object class includes at least one data member and at least one method. The hardware client transmits the object-oriented message generated to the object-oriented memory device via a hardware communications interface. The hardware communications interface couples the hardware client to the object-oriented memory device. The object is instantiated or to-be instantiated in at least one physical memory of the object-oriented memory device according to the object class. The at least one method enables the object-oriented memory device to access the at least one data member for the hardware client.

公开(公告)号：US11727254B2

公开(公告)日：2023-08-15

申请号：US17005140

申请日：2020-08-27

申请人： Cerebras Systems Inc.

发明人： Sean Lie ,  Gary R. Lauterbach ,  Michael Edwin James ,  Michael Morrison ,  Srikanth Arekapudi

IPC分类号： G06N3/063 ,  G06F13/00 ,  G06N3/084 ,  G06N3/08 ,  G06F9/30 ,  H04L49/00 ,  G06F9/38 ,  H04L12/54 ,  G06F5/06 ,  G06F13/40 ,  G06N3/04 ,  G06N3/044 ,  G06N3/045 ,  G06N3/047 ,  G06N3/048 ,  H04L49/506 ,  G06F30/392

CPC分类号： G06N3/063 ,  G06F5/06 ,  G06F9/3001 ,  G06F9/3009 ,  G06F9/30014 ,  G06F9/3016 ,  G06F9/30036 ,  G06F9/30087 ,  G06F9/30192 ,  G06F9/3851 ,  G06F13/00 ,  G06F13/4027 ,  G06N3/04 ,  G06N3/044 ,  G06N3/045 ,  G06N3/047 ,  G06N3/048 ,  G06N3/08 ,  G06N3/084 ,  H04L12/56 ,  H04L49/3018 ,  G06F30/392 ,  H04L49/3045 ,  H04L49/506

摘要： Techniques in advanced deep learning provide improvements in one or more of accuracy, performance, and energy efficiency. An array of processing elements performs flow based computations on wavelets of data. Each processing element has a compute element and a routing element. Each compute element has memory. Each router enables communication via wavelets with nearest neighbors in a 2D mesh. A compute element receives a wavelet. If a control specifier of the wavelet is a first value, then instructions are read from the memory of the compute element in accordance with an index specifier of the wavelet. If the control specifier is a second value, then instructions are read from the memory of the compute element in accordance with a virtual channel specifier of the wavelet. Then the compute element initiates execution of the instructions.

公开(公告)号：US11715529B2

公开(公告)日：2023-08-01

申请号：US17689300

申请日：2022-03-08

申请人： KIOXIA CORPORATION

发明人： Shinya Okuno ,  Shigeki Nagasaka ,  Toshiyuki Kouchi

IPC分类号： G11C16/04 ,  G11C16/32 ,  G11C16/26 ,  G11C16/16 ,  G11C16/12 ,  G11C7/02 ,  G11C7/10 ,  G11C16/10 ,  G06F5/06 ,  G06F13/16

CPC分类号： G11C16/32 ,  G06F5/06 ,  G06F13/1673 ,  G11C7/02 ,  G11C7/106 ,  G11C7/1012 ,  G11C7/1039 ,  G11C7/1066 ,  G11C16/10 ,  G11C16/12 ,  G11C16/16 ,  G11C16/26 ,  G06F2205/067 ,  G11C16/0483 ,  G11C2207/108 ,  G11C2207/2281 ,  Y02D10/00

摘要： A semiconductor device includes a memory circuit, a first FIFO, a second FIFO and an input/output circuit. The memory circuit outputs data. The first FIFO receives data from the memory circuit and outputs data synchronously with a first clock signal. The second FIFO receives data output from the first FIFO and outputs data synchronously with the first clock signal. The input/output circuit outputs data output from the second FIFO. The second FIFO is disposed in the vicinity of the input/output circuit than the first FIFO.

公开(公告)号：US20230214185A1

公开(公告)日：2023-07-06

申请号：US17564091

申请日：2021-12-28

申请人： Microsoft Technology Licensing, LLC

发明人： Karthikeyan AVUDAIYAPPAN ,  Jeffrey A. ANDREWS

IPC分类号： G06F7/544 ,  G06F5/06

CPC分类号： G06F7/5443 ,  G06F5/06

摘要： Embodiments of the present disclosure include a multipurpose multiply-accumulator (MAC) array circuit comprising one or more input memories for receiving operands and a plurality of multiply-accumulator circuits each selectively coupled to the one or more input memories to receive at least a pair of operands and generate a result. Each of the plurality of multiply-accumulator circuits receives operands from the one or more input memories independently. Additionally, selection of operands from the one or more input memories is controlled based on at least an operation and/or data types, where different operation and/or data types configure the plurality of multiply-accumulator circuits to receive different pairs of operands from the one or more input memories to execute particular operation types.

公开(公告)号：US11687363B2

公开(公告)日：2023-06-27

申请号：US16855510

申请日：2020-04-22

申请人： Micron Technology, Inc.

发明人： Fangfang Zhu ,  Ying Yu Tai ,  Ning Chen ,  Jiangli Zhu ,  Wei Wang

IPC分类号： G06F9/48 ,  G06F9/50 ,  G06F9/54 ,  G06F11/30 ,  G06F11/34 ,  G06F13/16 ,  G06F5/06 ,  G06F3/06

CPC分类号： G06F9/4881 ,  G06F3/0659 ,  G06F5/06 ,  G06F9/5016 ,  G06F9/546 ,  G06F11/3037 ,  G06F11/3409 ,  G06F11/3433 ,  G06F13/1673 ,  G06F13/1694 ,  G06F2201/81 ,  G06F2209/5022

摘要： In one embodiment, a processing device is coupled to memory components to monitor host read operations and host write operations from a host device coupled to the plurality of memory components. The processing device schedules, using a variable size internal command queue, a predetermined proportion of back-end processing device read and write operations as internal management traffic proportional to a number of the host read operations and a number of the host write operations. The processing device then executes a subset of the host read operations and the host write operations. Following execution of the subset of the host read operations and the host write operations, the processing device executes an internal management traffic operation based on the predetermined proportion.

公开(公告)号：US20230124740A1

公开(公告)日：2023-04-20

申请号：US17909498

申请日：2020-09-28

申请人： INSPUR SUZHOU INTELLIGENT TECHNOLOGY CO., LTD.

发明人： Xiuqiang SUN

IPC分类号： G06F13/40 ,  G06F13/16 ,  G06F5/06

摘要： A method for supporting TCM communication by a BIOS of an ARM server, including: setting an access mode of a LPC bus device to a 4-byte mode by means of a BIOS of an ARM server; causing the BIOS to perform data communication with a TCM chip of the LPC bus device in the 4-byte mode; in response to the BIOS reading a register by means of the LPC bus device, determining a type of the register; in response to determining that the type of the register is a specific FIFO register, changing a control register from the 4-byte mode to a single-byte mode, and performing single-byte read-write on the specific FIFO register; and in response to completion of read-write of the specific FIFO register, changing the control register to the 4-byte mode by means of the BIOS, and performing a read-write operation on other FIFO registers.

公开(公告)号：US20230115533A1

公开(公告)日：2023-04-13

申请号：US17484415

申请日：2021-09-24

申请人： International Business Machines Corporation

发明人： Patrick James Meaney ,  Ashutosh Mishra ,  Paul Allen Ganfield ,  Christian Jacobi ,  Logan Ian Friedman ,  Jentje Leenstra ,  Glenn David Gilda ,  Michael B. Spear

IPC分类号： G06F11/14 ,  G06F11/07 ,  G06F13/38 ,  G06F13/28 ,  G06F5/06

摘要： Embodiments of the invention are directed to a computer-implemented method of operating a data transmission system. The data transmission system includes a transmitter and a receiver. The computer-implemented method includes using the transmitter to send serialized data from the transmitter through a plurality of lanes to the receiver. The transmitter sends the serialized data at a first serialization ratio. The receiver is configured to receive and load the serialized data at a second deserialization ratio, wherein the first serialization ration is greater than the second deserialization ratio.

公开(公告)号：US11583794B2

公开(公告)日：2023-02-21

申请号：US16487940

申请日：2018-02-22

申请人： Cummins Filtration IP, Inc.

发明人： Abhijeet Vaidya ,  Erica C. Clark-Heinrich ,  Amit Dhingra ,  Bharadwaj R. Prabhala

IPC分类号： B01D37/04 ,  B01D35/143 ,  G06F5/06 ,  G05D1/00

摘要： Data relating to the status of a vehicle, an internal combustion engine powering the vehicle, and various filtration systems that provide filtered fluid to the vehicle and/or internal combustion engine is generated or gathered by an engine control module and a filtration monitoring system. The engine control module and the filtration monitoring system provide the data to a telematics system for transmitting the data to a remote data center (e.g., a cloud computing system, a remote diagnostics system, a maintenance system, etc.). Depending on an availability of a cellular data connection, the data is either sent directly to the remote data center via a network, or indirectly by first transmitting the data over a local connection to an operator device (e.g., a smartphone), which then sends the data to the remote data center once a connection to the network is available.

公开(公告)号：US11561765B2

公开(公告)日：2023-01-24

申请号：US17384496

申请日：2021-07-23

申请人： Intel Corporation

发明人： John Howard ,  Steven B. McGowan ,  Krzysztof Perycz

IPC分类号： G06F5/06 ,  G06F13/28 ,  G06F13/16 ,  G06F13/40 ,  G06F5/14

摘要： An apparatus for managing input/output (I/O) data may include a streaming I/O controller to receive data from a load/store domain component and output the data as first streaming data of a first data type comprising a first data movement type and first data format type. The apparatus may also include at least one accelerator coupled to the streaming I/O controller to receive the first streaming data, transform the first streaming data to second streaming data having a second data type different than the first data type, and output the second streaming data. In addition, the apparatus may include a streaming interconnect to conduct the second data to a peer device configured to receive data of the second data type.

公开(公告)号：US20220366960A1

公开(公告)日：2022-11-17

申请号：US17852286

申请日：2022-06-28

申请人： Rambus Inc.

发明人： Thomas J. Giovannini ,  Alok Gupta ,  Ian Shaeffer ,  Steven C. Woo

IPC分类号： G11C11/4076 ,  G06F3/06 ,  G06F5/06 ,  G06F1/08 ,  G11C7/10 ,  G11C29/02 ,  G06F13/16 ,  G06F12/06 ,  G11C11/409

摘要： A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to calibrate a phase relationship between a data-strobe signal and a clock signal received at the memory chip from the memory controller during a write operation. Furthermore, the memory controller is configured to perform one or more write-read-validate operations to calibrate a clock-cycle relationship between the data-strobe signal and the clock signal, wherein the write-read-validate operations involve varying a delay on the data-strobe signal relative to the clock signal by a multiple of a clock period.