公开(公告)号：US12028276B2

公开(公告)日：2024-07-02

申请号：US17409889

申请日：2021-08-24

申请人： International Business Machines Corporation

发明人： Pasquale A. Catalano ,  Michael James Becht ,  Christopher J. Colonna ,  Stephen Robert Guendert

IPC分类号： H04L49/20 ,  H04L49/00 ,  H04L49/90

CPC分类号： H04L49/208 ,  H04L49/3045 ,  H04L49/90

摘要： Aspects include includes receiving, at an input/output (I/O) processor, a transport control word (TCW) that includes an instruction to perform virtual port mirroring. The I/O processor identifies a first port to be mirrored and a virtual port to perform the mirroring. The virtual port is a first memory location in a memory. In response to outbound data being sent to the first port for transmission to a first target device and to the instruction specifying outbound port mirroring, the I/O processor stores a copy of the outbound data in the first memory location. In response to inbound data being received at the first port and to the instruction specifying inbound port mirroring, a copy of the inbound data is stored at the first memory location.

公开(公告)号：US20180212889A1

公开(公告)日：2018-07-26

申请号：US15415329

申请日：2017-01-25

申请人： Futurewei Technologies, Inc.

发明人： Wei Xu ,  Xiaofeng Yang ,  Yan Sun ,  Yizhen Liu ,  Zhe Fu ,  Zhi Liu ,  Jun Li

IPC分类号： H04L12/851 ,  H04L12/935 ,  H04L12/819 ,  H04L12/863

CPC分类号： H04L47/2441 ,  H04L47/215 ,  H04L47/6295 ,  H04L49/3045

摘要： An apparatus, such as a network element, comprises a receiver to receive a plurality of packets. A memory stores instructions and forms a first and second set of virtual queues to store the plurality of packets. A processor having one or more cores with one or more packet classifiers provides a classification of a packet in the plurality of packets. The processor in communication with the memory executes instructions to transfer the packet from the receiver to a virtual queue in the first set of virtual queues based on the classification. The processor also transfers the packet from the virtual queue to a transmitter based on a demand rate value and supply rate value associated with the virtual queue.

公开(公告)号：US10009295B2

公开(公告)日：2018-06-26

申请号：US15817180

申请日：2017-11-18

申请人： Fortinet, Inc.

发明人： Xu Zhou ,  David Chen ,  Lin Huang ,  Guansong Zhang

IPC分类号： H04L12/935 ,  H04L29/06 ,  H04L12/863 ,  G06F13/16 ,  G06F12/1081

CPC分类号： H04L69/166 ,  G06F12/1081 ,  G06F13/1689 ,  G06F2212/651 ,  G06F2212/657 ,  H04L47/62 ,  H04L47/621 ,  H04L49/3045

摘要： Methods and systems for a more efficient transmission of network traffic are provided. According to one embodiment, presence of outbound payload data, distributed across a first and second payload buffer, within a user memory space of a network device that has been generated by a user process is determined by a bus/memory interface or a network interface unit. The payload data is fetched by performing direct virtual memory addressing of the user memory space including mapping virtual addresses of the payload buffers to corresponding physical addresses, including: (i) when the payload buffers are noncontiguous, then retrieving the outbound payload data with reference to multiple buffer descriptors having starting virtual addresses of the payload buffers and (ii) when they are contiguous, then retrieving the outbound payload data with reference to a single buffer descriptor. The outbound payload data is then segmented across one or more TCP packets.

公开(公告)号：US20170353400A1

公开(公告)日：2017-12-07

申请号：US15680866

申请日：2017-08-18

申请人： Tadeusz H. Szymanski

发明人： Tadeusz H. Szymanski

IPC分类号： H04L12/933 ,  H04L12/937 ,  H04L12/911 ,  H04L12/935 ,  H04L12/873

CPC分类号： H04L49/101 ,  H04L47/528 ,  H04L47/72 ,  H04L49/254 ,  H04L49/3045

摘要： A crossbar switch has N input ports, M output ports, and a switching matrix with N×M crosspoints. In an embodiment, each crosspoint contains an internal queue (XQ), which can store one or more packets to be routed. Traffic rates to be realized between all Input/Output (IO) pairs of the switch are specified in an N×M traffic rate matrix, where each element equals a number of requested cell transmission opportunities between each IO pair within a scheduling frame of F time-slots. An efficient algorithm for scheduling N traffic flows with traffic rates based upon a recursive and fair decomposition of a traffic rate vector with N elements, is proposed. To reduce memory requirements a shared row queue (SRQ) may be embedded in each row of the switching matrix, allowing the size of all the XQs to be reduced. To further reduce memory requirements, a shared column queue may be used in place of the XQs. The proposed buffered crossbar switches with shared row and column queues, in conjunction with the row scheduling algorithm and the DCS column scheduling algorithm, can achieve high throughput with reduced buffer and VLSI area requirements, while providing probabilistic guarantees on rate, delay and jitter for scheduled traffic flows.

公开(公告)号：US20170187614A1

公开(公告)日：2017-06-29

申请号：US14979667

申请日：2015-12-28

申请人： Mellanox Technologies TLV Ltd.

发明人： Zachy Haramaty ,  Eitan Zahavi ,  Itamar Rabenstein

IPC分类号： H04L12/753 ,  H04L12/44 ,  H04L12/741 ,  H04L12/935

CPC分类号： H04L45/48 ,  H04L12/44 ,  H04L12/4625 ,  H04L45/74 ,  H04L49/3045

摘要： A switch includes multiple physical ports and forwarding circuitry. The physical ports are configured to receive and send packets over a network. The forwarding circuitry is configured to assign first port numbers to the physical ports, and second port numbers to temporary ports defined in addition to the physical ports, to receive a packet having a destination address via a physical port, to select, based on the destination address, an egress port number for the packet from among the first and second port numbers, to forward the packet to a physical port corresponding to the egress port number if the egress port number is one of the first port numbers, and, if the egress port number is one of the second port numbers, to map a temporary port associated with the egress port number to a mapped physical port and to forward the packet to the mapped physical port.

公开(公告)号：US20170149694A1

公开(公告)日：2017-05-25

申请号：US14946907

申请日：2015-11-20

申请人： Cisco Technology, Inc.

发明人： Yegappan Lakshmanan ,  Atulya Chandra ,  Nagaraj Arunkumar

IPC分类号： H04L12/935

CPC分类号： H04L49/3045

摘要： An emulator module integrated with a hypervisor executes on a host computer having a physical network interface card (pNIC). The hypervisor hosts a virtual machine having a virtual NIC (vNIC). The pNIC has pNIC receive pointers to point to receive packets loaded into a receive buffer by the pNIC. The vNIC has vNIC receive pointers for retrieval of the receive packets from the receive buffer. The emulator module accesses a pNIC receive pointer in the pNIC that points to the receive packet loaded into the receive buffer by the pNIC, and maps a vNIC receive pointer to the pNIC receive pointer accessed by the emulator module, to enable the vNIC to retrieve the receive packet from the receive buffer using the vNIC receive pointer. The emulator module notifies the vNIC to retrieve the receive packet from the receive buffer.

公开(公告)号：US20170118033A1

公开(公告)日：2017-04-27

申请号：US14919409

申请日：2015-10-21

申请人： Oracle International Corporation

发明人： Arvind Srinivasan

IPC分类号： H04L12/18 ,  H04L12/935 ,  H04L12/24 ,  H04L12/947 ,  H04L12/761

CPC分类号： H04L12/18 ,  H04L41/0893 ,  H04L49/25 ,  H04L49/3045

摘要： A system for communicating a multicast packet through a network switch fabric is described. The system receives the multicast packet at an input port of the network switch fabric, where the multicast packet is directed to multiple output ports, and where the network switch fabric has a virtual output queue (VOQ)-based architecture, in which each input port maintains a separate VOQ for unicast packets to each output port and one or more VOQs for multicast packets destined to multiple output ports. The system sends the multicast packet by inserting the multicast packet into the one or more VOQs associated with the multiple output ports, so that multicast packets are queued separately from unicast packets. Moreover, the system may optionally dynamically modify a number of the one or more VOQs for the multicast packets based on a number of multicast flows through the network switch fabric.

公开(公告)号：US20160294698A1

公开(公告)日：2016-10-06

申请号：US15085337

申请日：2016-03-30

申请人： Telefonica, S.A.

发明人： Ignacio BERBERANA FERNANDEZ-MURIAS

IPC分类号： H04L12/801 ,  H04L12/825

CPC分类号： H04L47/12 ,  H04L47/24 ,  H04L47/2441 ,  H04L47/25 ,  H04L49/3045

摘要： The method comprises identifying and classifying, by a classification unit (102), received data packets flows between fixed bit rate data packets flows (FB) and variable bit rate data packets flows (VB); sending the identified and classified fixed bit rate data packets flows (FB) to a pacer unit (103) spacing the transmission of the fixed bit rate data packets flows (FB) towards an egress port of the transport node (100); and sending the configuration parameters relating to the variable bit rate data packets flows (VB) to a virtual queue unit (104), said virtual queue unit (104) including a processor running an algorithm to activate one or more congestion correction procedures, wherein in case the result obtained by said algorithm being over, or equal, at least one threshold activating a corresponding congestion correction procedure.

摘要翻译： 所述方法包括通过分类单元（102）识别和分类在固定比特率数据分组流（FB）和可变比特率数据分组流（VB）之间的接收数据分组流; 将所识别的和分类的固定比特率数据分组流（FB）发送到间隔单元（103），所述比赛单元将固定比特率数据分组流（FB）的传输间隔到所述传输节点（100）的出口端口; 以及将与所述可变比特率数据分组流（VB）相关的配置参数发送到虚拟队列单元（104），所述虚拟队列单元（104）包括运行用于激活一个或多个拥塞校正过程的算法的处理器，其中， 情况下，所述算法获得的结果超过或等于激活对应的拥塞校正过程的至少一个阈值。

公开(公告)号：US20160191404A1

公开(公告)日：2016-06-30

申请号：US14584824

申请日：2014-12-29

申请人： Oracle International Corporation

发明人： Arvind Srinivasan ,  Carlos Castil

IPC分类号： H04L12/873 ,  H04L12/935 ,  H04L12/933

CPC分类号： H04L47/527 ,  H04L47/39 ,  H04L49/101 ,  H04L49/3027 ,  H04L49/3045

摘要： A system and method can support efficient packet switching in a network environment. A networking device, such as a network switch, which includes a crossbar fabric, can be associated with a plurality of input ports and a plurality of output ports. Furthermore, the networking device operates to detect a link state change at an output port on the networking device. The output port can provide one or more credits to an output scheduler, and the output scheduler allows one or more packets targeting the output port to be dequeued from one or more virtual output queues, based on the one or more credits.

摘要翻译： 系统和方法可以支持网络环境中的有效数据包交换。 包括交叉结构的网络交换机等网络设备可以与多个输入端口和多个输出端口相关联。 此外，网络设备操作以检测网络设备上的输出端口处的链路状态改变。 输出端口可以向输出调度器提供一个或多个信用，并且输出调度器基于一个或多个信用，允许针对输出端口的一个或多个分组从一个或多个虚拟输出队列出出。

公开(公告)号：US20150370736A1

公开(公告)日：2015-12-24

申请号：US14838073

申请日：2015-08-27

申请人： International Business Machines Corporation

发明人： Jeffrey D. Brown ,  Robert A. Shearer

IPC分类号： G06F13/362

CPC分类号： G06F13/362 ,  G06F13/14 ,  G06F13/3625 ,  H04L47/781 ,  H04L49/3045 ,  H04L2012/5679 ,  H04L2012/5681

摘要： A method for communicating data in a processing architecture comprising a plurality of interconnected IP blocks. Transmitting IP blocks may transmit messages to a shared receive queue for a first IP block. Receipt of the messages at the shared receive queue may be controlled based on receive credits allocated to each transmitting IP block. The allocation of receive credits for each transmitting IP block may dynamically managed such that the allocation of receive credits may be dynamically adjusted for each transmitting IP block based at least in part on message traffic associated with each transmitting IP block and/or a priority associated with each transmitting IP block.

摘要翻译： 一种用于在包括多个互连IP块的处理架构中传送数据的方法。 发送IP块可以向第一IP块的共享接收队列发送消息。 可以基于分配给每个发送IP块的接收信用来控制在共享接收队列处的消息的接收。 可以动态地管理每个发送IP块的接收信用的分配，使得可以至少部分地基于与每个发送IP块相关联的消息流量和/或与每个发送IP块相关联的优先级来对每个发送IP块动态地调整接收信用的分配 每个发送IP块。