公开(公告)号：US20180174942A1

公开(公告)日：2018-06-21

申请号：US15576850

申请日：2016-01-29

Applicant: SOUTHEAST UNIVERSITY

Inventor： Siyang LIU ,  Ning WANG ,  Jiaxing WEI ,  Chao LIU ,  Weifeng SUN ,  Shengli LU ,  Longxing SHI

IPC: H01L23/367 ,  H01L25/18 ,  H01L23/31 ,  H01L23/495 ,  H01L25/16

CPC classification number: H01L23/3675 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/367 ,  H01L23/4334 ,  H01L23/49503 ,  H01L23/49537 ,  H01L23/49541 ,  H01L23/49562 ,  H01L23/49568 ,  H01L23/49575 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/16 ,  H01L25/18 ,  H01L2224/29139 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48175 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/01079 ,  H01L2924/1306 ,  H01L2924/1426 ,  H01L2924/17738 ,  H01L2924/17747 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A power module of a square flat pin-free packaging structure for suppressing the power module from being excessively high in local temperature. The power module includes an insulating resin, a driving chip, a plurality of power chips, and a plurality of metal electrode contacts. The driving chip, the power chips, and the metal electrode contacts are electrically connected through a metal lead according to a predetermined circuit. A plurality of metal heat dissipating disks used for heat dissipation of the power chips and a driving chip lead frame are disposed at the bottom of the insulating resin. A plurality of metal power chip lead frames are disposed on the metal heat dissipating disks, the power chips are disposed on the power chip lead frames, and the drain electrodes of the power chips are electrically connected to the metal heat dissipating disks.

公开(公告)号：US09932473B2

公开(公告)日：2018-04-03

申请号：US15075227

申请日：2016-03-21

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Emi Iwatani ,  Kazuto Ogawa ,  Kota Ishikawa ,  Takayuki Tsuji

IPC: C08L63/00 ,  C08J3/00 ,  H01L23/29 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56 ,  H01L23/495

CPC classification number: C08L63/00 ,  C08L2203/206 ,  C08L2205/03 ,  H01L21/565 ,  H01L23/293 ,  H01L23/295 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/49555 ,  H01L23/49582 ,  H01L24/48 ,  H01L24/85 ,  H01L2224/32245 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45565 ,  H01L2224/45664 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01016 ,  H01L2924/01028 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/06 ,  H01L2924/066 ,  H01L2924/0665 ,  H01L2924/17738 ,  H01L2924/17763 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: An encapsulating resin composition contains a thermosetting resin component, a curing accelerator, an inorganic filler, an ion trapping agent, and an aromatic monocarboxylic acid having one or more electron-withdrawing functional groups selected from a nitro group and a cyano group. The encapsulating resin composition is solid at 25° C., and has a sulfur content, measured by X-ray fluorescence analysis, of 0.1 mass % or less in terms of SO3.

公开(公告)号：US09917036B2

公开(公告)日：2018-03-13

申请号：US14827361

申请日：2015-08-17

Applicant: Infineon Technologies AG

Inventor： Georg Meyer-Berg

IPC: H01L23/043 ,  H01L23/495 ,  H01L21/56 ,  H01L23/00 ,  H01L21/48 ,  H01L25/065 ,  H01L23/31

CPC classification number: H01L23/49513 ,  H01L21/4821 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/49541 ,  H01L23/49575 ,  H01L23/49582 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/32 ,  H01L24/82 ,  H01L25/0655 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/24155 ,  H01L2224/29082 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29155 ,  H01L2224/29164 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/82007 ,  H01L2924/01028 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/06 ,  H01L2924/0665 ,  H01L2924/07025 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/1715 ,  H01L2924/17738 ,  H01L2924/17747 ,  H01L2924/1776 ,  H01L2924/17763 ,  H01L2924/181 ,  H01L2924/2064 ,  H01L2924/20641 ,  H01L2924/20642 ,  H01L2924/20643 ,  H01L2924/20644 ,  H01L2924/20645 ,  H01L2924/20646 ,  H01L2924/20647 ,  H01L2924/20648 ,  H01L2924/20649 ,  H01L2924/2065 ,  H01L2924/00

Abstract: Various embodiments provide for a chip package consisting of a layer over a carrier, further carrier material over the layer, wherein one or more portions of the further carrier material is removed, and a chip with one or more contact pads, where the chip is adhered to the carrier via the layer. A wafer level package consisting of a plurality of chips adhered to the carrier via a plurality of portions of the layer released from the further carrier material is also provided for.

公开(公告)号：US09111847B2

公开(公告)日：2015-08-18

申请号：US13523942

申请日：2012-06-15

Applicant: Georg Meyer-Berg

Inventor： Georg Meyer-Berg

IPC: H01L21/00 ,  H01L23/00 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L23/49513 ,  H01L21/4821 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/49541 ,  H01L23/49575 ,  H01L23/49582 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/32 ,  H01L24/82 ,  H01L25/0655 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/24155 ,  H01L2224/29082 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29155 ,  H01L2224/29164 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/82007 ,  H01L2924/01028 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/06 ,  H01L2924/0665 ,  H01L2924/07025 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/1715 ,  H01L2924/17738 ,  H01L2924/17747 ,  H01L2924/1776 ,  H01L2924/17763 ,  H01L2924/181 ,  H01L2924/2064 ,  H01L2924/20641 ,  H01L2924/20642 ,  H01L2924/20643 ,  H01L2924/20644 ,  H01L2924/20645 ,  H01L2924/20646 ,  H01L2924/20647 ,  H01L2924/20648 ,  H01L2924/20649 ,  H01L2924/2065 ,  H01L2924/00

Abstract: A method for manufacturing a chip package is provided. The method includes forming a layer over a carrier; forming further carrier material over the layer; selectively removing one or more portions of the further carrier material thereby releasing one or more portions of the layer from the further carrier material; and adhering a chip including one or more contact pads to the carrier via the layer.

Abstract translation: 提供了一种制造芯片封装的方法。 该方法包括在载体上形成层; 在该层上形成另外的载体材料; 选择性地去除所述另外的载体材料的一个或多个部分，从而将所述层的一个或多个部分从所述另外的载体材料释放; 以及通过所述层将包括一个或多个接触焊盘的芯片粘附到所述载体。

公开(公告)号：US20130026490A1

公开(公告)日：2013-01-31

申请号：US13194585

申请日：2011-07-29

Applicant: Victor H. Cruz ,  David Francis Courtney

Inventor： Victor H. Cruz ,  David Francis Courtney

IPC: H01L21/56 ,  H01L29/20 ,  H01L29/12 ,  H01L23/495

CPC classification number: H01L23/291 ,  H01L23/3107 ,  H01L23/49513 ,  H01L23/49524 ,  H01L23/49541 ,  H01L23/49562 ,  H01L23/49582 ,  H01L24/05 ,  H01L24/06 ,  H01L24/29 ,  H01L24/32 ,  H01L24/34 ,  H01L24/36 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/04026 ,  H01L2224/04042 ,  H01L2224/05639 ,  H01L2224/05655 ,  H01L2224/06181 ,  H01L2224/29139 ,  H01L2224/29147 ,  H01L2224/32245 ,  H01L2224/37184 ,  H01L2224/37639 ,  H01L2224/37655 ,  H01L2224/40247 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/48247 ,  H01L2224/4847 ,  H01L2224/48699 ,  H01L2224/48739 ,  H01L2224/48755 ,  H01L2224/83439 ,  H01L2224/83455 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2224/85439 ,  H01L2224/85455 ,  H01L2224/92246 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00011 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01047 ,  H01L2924/097 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/15747 ,  H01L2924/15787 ,  H01L2924/17738 ,  H01L2924/181 ,  H01L2924/186 ,  H01L2924/201 ,  H01L2924/20111 ,  H01L2224/84 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/01049 ,  H01L2924/00014 ,  H01L2924/01005

Abstract: A high temperature, non-cavity package for non-axial electronics is designed using a glass ceramic compound with that is capable of being assembled and operating continuously at temperatures greater that 300-400° C. Metal brazes, such as silver, silver colloid or copper, are used to connect the semiconductor die, lead frame and connectors. The components are also thermally matched such that the packages can be assembled and operating continuously at high temperatures and withstand extreme temperature variations without the bonds failing or the package cracking due to a thermal mismatch.

Abstract translation: 用于非轴向电子器件的高温非空腔封装是使用玻璃陶瓷化合物设计的，其能够在高于300-400℃的温度下连续组装和操作。金属钎焊，例如银，银胶体或 铜，用于连接半导体管芯，引线框架和连接器。 这些部件也是热匹配的，使得封装可以在高温下连续地组装和操作，并且可承受极端的温度变化，而不会发生键失效或者由于热失配引起的封装破裂。

公开(公告)号：US20120286412A1

公开(公告)日：2012-11-15

申请号：US13522853

申请日：2011-01-17

Applicant: Akihiro Kimura ,  Tsunemori Yamaguchi

Inventor： Akihiro Kimura ,  Tsunemori Yamaguchi

IPC: H01L23/495 ,  H01L21/78

CPC classification number: H01L23/49513 ,  H01L23/3107 ,  H01L23/3135 ,  H01L23/49503 ,  H01L23/49541 ,  H01L23/49551 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/83385 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/0133 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/17738 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/01015 ,  H01L2924/01026 ,  H01L2924/01028 ,  H01L2924/3512

Abstract: A semiconductor device 100 includes a first insulating material 110 attached to a second main surface 106b of a semiconductor chip 106, and a second insulating material 112 attached to side surfaces of the semiconductor chip 106, the first insulating material 110 and an island 102. The semiconductor chip 106 is fixed to the island 102 via the first insulating material 110 and the second insulating material 112. The first insulating material 110 ensures a high dielectric strength between the semiconductor chip 106 and the island 102. Though the second insulating material 112 having a modulus of elasticity greater than that of the first insulating material 110, the semiconductor chip 106 is firmly attached to the island 102.

Abstract translation: 半导体器件100包括附接到半导体芯片106的第二主表面106b的第一绝缘材料110和附接到半导体芯片106，第一绝缘材料110和岛102的侧表面的第二绝缘材料112。 半导体芯片106经由第一绝缘材料110和第二绝缘材料112固定到岛102.第一绝缘材料110确保半导体芯片106和岛102之间的高介电强度。虽然第二绝缘材料112具有 弹性模量大于第一绝缘材料110的弹性模量，半导体芯片106牢固地附接到岛102。

公开(公告)号：US20180158804A1

公开(公告)日：2018-06-07

申请号：US15367694

申请日：2016-12-02

Applicant: Dialog Semiconductor (UK) Limited

Inventor： Melvin Martin ,  Baltazar Canete, JR. ,  Macario Campos ,  Rajesh Aiyandra

IPC: H01L25/07 ,  H01L23/492 ,  H01L23/495 ,  H01L23/00 ,  H01L23/482 ,  H01L25/00 ,  H01L23/367 ,  H01L25/18

CPC classification number: H01L25/072 ,  H01L23/482 ,  H01L23/492 ,  H01L23/49524 ,  H01L23/49555 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48096 ,  H01L2224/48106 ,  H01L2224/48247 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/10161 ,  H01L2924/1302 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/1425 ,  H01L2924/17724 ,  H01L2924/17738 ,  H01L2924/17747 ,  H01L2924/19105 ,  H01L2924/00014

Abstract: An integrated circuit IC package with one or more pins protruding from the IC package for electrically connecting the IC package with a printed circuit board PCB is presented. The IC package has a first die with a first electronic component, a second die with a second electronic component, and a conductive plate having a plane surface. The first electronic component may be a semiconductor power device and the second electronic component may be a control circuit. The plane surface of the conductive plate is electrically connected to both a plane surface of the first die and one or more pins such that an electrical connection is established between the first die and the one or more pins. The second die may be arranged on top of the conductive plate. Alternatively, a third die with a third electronic component may be arranged on top of the conductive plate.

公开(公告)号：US20180158759A1

公开(公告)日：2018-06-07

申请号：US15883151

申请日：2018-01-30

Applicant: Infineon Technologies AG

Inventor： Georg MEYER-BERG

IPC: H01L23/495 ,  H01L21/56 ,  H01L23/00 ,  H01L25/065 ,  H01L21/48 ,  H01L23/31

CPC classification number: H01L23/49513 ,  H01L21/4821 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/49541 ,  H01L23/49575 ,  H01L23/49582 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/32 ,  H01L24/82 ,  H01L25/0655 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/24155 ,  H01L2224/29082 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29155 ,  H01L2224/29164 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/82007 ,  H01L2924/01028 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/06 ,  H01L2924/0665 ,  H01L2924/07025 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/1715 ,  H01L2924/17738 ,  H01L2924/17747 ,  H01L2924/1776 ,  H01L2924/17763 ,  H01L2924/181 ,  H01L2924/2064 ,  H01L2924/20641 ,  H01L2924/20642 ,  H01L2924/20643 ,  H01L2924/20644 ,  H01L2924/20645 ,  H01L2924/20646 ,  H01L2924/20647 ,  H01L2924/20648 ,  H01L2924/20649 ,  H01L2924/2065 ,  H01L2924/00

Abstract: Various embodiments provide for a chip package including a carrier; a layer over the carrier; a further carrier material over the layer, the further carrier material comprising a foil; one or more openings in the further carrier material, wherein the one or more openings expose at least one or more portions of the layer from the further carrier material; and a chip comprising one or more contact pads, wherein the chip is adhered to the carrier via the one or more exposed portions of the layer.

公开(公告)号：US09859194B2

公开(公告)日：2018-01-02

申请号：US15208349

申请日：2016-07-12

Applicant: ROHM CO., LTD.

Inventor： Akihiro Kimura ,  Tsunemori Yamaguchi

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/495

CPC classification number: H01L23/49513 ,  H01L23/3107 ,  H01L23/3135 ,  H01L23/49503 ,  H01L23/49541 ,  H01L23/49551 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/83385 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/0133 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/17738 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/01015 ,  H01L2924/01026 ,  H01L2924/01028 ,  H01L2924/3512

Abstract: A semiconductor device 100 includes a first insulating material 110 attached to a second main surface 106b of a semiconductor chip 106, and a second insulating material 112 attached to side surfaces of the semiconductor chip 106, the first insulating material 110 and an island 102. The semiconductor chip 106 is fixed to the island 102 via the first insulating material 110 and the second insulating material 112. The first insulating material 110 ensures a high dielectric strength between the semiconductor chip 106 and the island 102. Though the second insulating material 112 having a modulus of elasticity greater than that of the first insulating material 110, the semiconductor chip 106 is firmly attached to the island 102.

公开(公告)号：US09406591B2

公开(公告)日：2016-08-02

申请号：US14824297

申请日：2015-08-12

Applicant: ROHM CO., LTD.

Inventor： Akihiro Kimura ,  Tsunemori Yamaguchi

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/495

CPC classification number: H01L23/49513 ,  H01L23/3107 ,  H01L23/3135 ,  H01L23/49503 ,  H01L23/49541 ,  H01L23/49551 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/83385 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/0133 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/17738 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/01015 ,  H01L2924/01026 ,  H01L2924/01028 ,  H01L2924/3512

Abstract: A semiconductor device 100 includes a first insulating material 110 attached to a second main surface 106b of a semiconductor chip 106, and a second insulating material 112 attached to side surfaces of the semiconductor chip 106, the first insulating material 110 and an island 102. The semiconductor chip 106 is fixed to the island 102 via the first insulating material 110 and the second insulating material 112. The first insulating material 110 ensures a high dielectric strength between the semiconductor chip 106 and the island 102. Though the second insulating material 112 having a modulus of elasticity greater than that of the first insulating material 110, the semiconductor chip 106 is firmly attached to the island 102.