公开(公告)号：US12087723B2

公开(公告)日：2024-09-10

申请号：US18111328

申请日：2023-02-17

Applicant: Infineon Technologies Austria AG

Inventor： Victor Verdugo ,  Katrin Schmidt ,  Steffen Schmidt ,  Markus Schmitt

IPC: H01L23/00 ,  B23K1/00 ,  H01L29/417 ,  H01L29/45 ,  H01L29/51 ,  B23K101/40

CPC classification number: H01L24/32 ,  B23K1/0016 ,  H01L24/83 ,  H01L29/41741 ,  H01L29/456 ,  H01L29/51 ,  B23K2101/40 ,  H01L2224/29083 ,  H01L2224/29166 ,  H01L2224/29184 ,  H01L2224/29205 ,  H01L2224/29209 ,  H01L2224/29211 ,  H01L2224/29213 ,  H01L2224/29217 ,  H01L2224/29218 ,  H01L2224/2922 ,  H01L2224/29239 ,  H01L2224/29244 ,  H01L2224/29247 ,  H01L2224/32227 ,  H01L2224/32245 ,  H01L2224/32503 ,  H01L2224/83201 ,  H01L2224/83203 ,  H01L2224/8321 ,  H01L2224/8381 ,  H01L2224/8382

Abstract: A semiconductor assembly includes a substrate including a metal die attach surface, a semiconductor die that is arranged on the substrate, the semiconductor die being configured as a power semiconductor device and comprising a semiconductor body, a rear side metallization, and a front side layer stack, the front side layer stack comprising a front side metallization and a contaminant protection layer that is between the front side metallization and the semiconductor body, and a diffusion soldered joint between the metal die attach surface and the rear side metallization, the diffusion soldered joint comprising one or more intermetallic phases throughout the diffusion soldered joint, wherein the contaminant protection layer is configured to prevent transmission of contaminants into the semiconductor body.

公开(公告)号：US11887960B2

公开(公告)日：2024-01-30

申请号：US16757798

申请日：2018-10-23

Applicant: HITACHI CHEMICAL COMPANY, LTD.

Inventor： Motohiro Negishi ,  Hideo Nakako ,  Yuki Kawana ,  Dai Ishikawa ,  Chie Sugama ,  Yoshinori Ejiri

IPC: H01L23/00 ,  B22F7/06 ,  B22F7/08 ,  B23K35/02 ,  B23K35/30 ,  B22F1/05 ,  B22F1/107 ,  B22F7/04 ,  B22F1/102 ,  B22F1/052

CPC classification number: H01L24/29 ,  B22F1/05 ,  B22F1/107 ,  B22F7/064 ,  B22F7/08 ,  B23K35/025 ,  B23K35/302 ,  H01L24/83 ,  B22F1/052 ,  B22F1/102 ,  B22F2007/047 ,  B22F2301/10 ,  B22F2304/10 ,  B22F2998/10 ,  H01L2224/29013 ,  H01L2224/29247 ,  H01L2224/8384 ,  B22F2998/00 ,  B22F1/068 ,  B22F1/065 ,  B22F2999/00 ,  B22F1/107 ,  C22C1/0425 ,  B22F2007/047

Abstract: This member connection method includes a printing step. In the printing step, a coating film-formed region in which the coating film is formed, and a coating film non-formed region in which the coating film is not formed are formed in the print pattern, and the coating film-formed region is divided into a plurality of concentric regions and a plurality of radial regions by means of a plurality of line-shaped regions provided so as to connect various points, which are separated apart from one another in the marginal part of the connection region.

公开(公告)号：US11856828B2

公开(公告)日：2023-12-26

申请号：US17498148

申请日：2021-10-11

Applicant: Samsung Display Co., Ltd.

Inventor： Joo-Nyung Jang

IPC: H10K59/131 ,  H01L23/00 ,  H10K59/12

CPC classification number: H10K59/131 ,  H01L24/29 ,  H01L24/83 ,  H01L2224/29239 ,  H01L2224/29244 ,  H01L2224/29247 ,  H01L2224/29255 ,  H01L2224/29257 ,  H01L2224/83851 ,  H01L2224/83862 ,  H01L2924/12044 ,  H10K59/1201

Abstract: A method of manufacturing a display device including the steps of providing a lower substrate having a display area and a pad area, forming a display structure in the display area of the lower substrate, forming pad electrodes in the pad area of the lower substrate to be spaced apart from each other in a first direction parallel to a top surface of the lower substrate, forming an upper substrate on the display structure to face the lower substrate in the display area, forming a conductive film member including a non-cured resin layer and conductive balls arranged in a lattice shape on the pad electrodes, the non-cured resin layer overlapping the pad electrodes, and forming a film package on the non-cured resin layer, the film package including bump electrodes overlapping the pad electrodes.

公开(公告)号：US11810885B2

公开(公告)日：2023-11-07

申请号：US17187452

申请日：2021-02-26

Applicant: WASEDA UNIVERSITY

Inventor： Kohei Tatsumi ,  Yasunori Tanaka

IPC: H01L23/00 ,  H01L23/495

CPC classification number: H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L23/49582 ,  H01L24/05 ,  H01L2224/05124 ,  H01L2224/27464 ,  H01L2224/29247 ,  H01L2224/29255 ,  H01L2224/29324 ,  H01L2224/29355 ,  H01L2224/32245 ,  H01L2224/8384 ,  H01L2224/83091 ,  H01L2224/83099 ,  H01L2224/83192 ,  H01L2224/83395 ,  H01L2224/83455 ,  H01L2224/83951 ,  H01L2924/10272 ,  H01L2924/15738 ,  H01L2924/15747 ,  H01L2924/3512

Abstract: A semiconductor element bonding structure capable of strongly bonding a semiconductor element and an object to be bonded and relaxing thermal stress caused by a difference in thermal expansion, by interposing metal particles and Ni between the semiconductor element and the object to be bonded, the metal particles having a lower hardness than Ni and having a micro-sized particle diameter. A plurality of metal particles 5 (aluminum (Al), for example) having a lower hardness than nickel (Ni) and having a micro-sized particle diameter are interposed between a semiconductor chip 3 and a substrate 2 to be bonded to the semiconductor chip 3, and the metal particles 5 are fixedly bonded by the nickel (Ni). Optionally, aluminum (Al) or an aluminum alloy (Al alloy) is used as the metal particles 5, and aluminum (Al) or an aluminum alloy (Al alloy) is used on the surface of the semiconductor chip 3 and/or the surface of the substrate 2.

公开(公告)号：US11710709B2

公开(公告)日：2023-07-25

申请号：US17228033

申请日：2021-04-12

Applicant: DENSO CORPORATION

Inventor： Ryoichi Kaizu ,  Takumi Nomura ,  Tetsuto Yamagishi ,  Yuki Inaba ,  Yoshitsugu Sakamoto

IPC: H01L23/31 ,  H01L23/495 ,  H01L23/00 ,  B23K35/26 ,  B23K35/30 ,  C22C12/00 ,  H02P27/06

CPC classification number: H01L23/562 ,  B23K35/264 ,  B23K35/30 ,  C22C12/00 ,  H01L23/3107 ,  H01L23/4952 ,  H01L23/49513 ,  H01L23/49562 ,  H01L23/49568 ,  H01L23/49575 ,  H01L23/49582 ,  H01L24/29 ,  H01L2224/2922 ,  H01L2224/29213 ,  H01L2224/29239 ,  H01L2224/29247 ,  H01L2224/29255 ,  H01L2924/014 ,  H01L2924/10272 ,  H01L2924/13091 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/3511 ,  H02P27/06

Abstract: A semiconductor device includes a semiconductor chip made of a SiC substrate and having main electrodes on one surface and a rear surface, first and second heat sinks, respectively, disposed adjacent to the one surface and the rear surface, a terminal member interposed between the second heat sink and the semiconductor chip, and a plurality of bonding members disposed between the main electrodes, the first and second heat sinks, and the terminal member. The terminal member includes plural types of metal layers symmetrically layered in the plate thickness direction. The terminal member as a whole has a coefficient of linear expansion at least in a direction orthogonal to the plate thickness direction in a range larger than that of the semiconductor chip and smaller than that of the second heat sink.

公开(公告)号：US20180166411A1

公开(公告)日：2018-06-14

申请号：US15797296

申请日：2017-10-30

Applicant: Panasonic Intellectual Property Management Co., Lt

Inventor： KIYOHIRO HINE ,  AKIO FURUSAWA ,  HIDETOSHI KITAURA ,  KAZUKI SAKAI

IPC: H01L23/00 ,  B23K35/26 ,  C22C13/00

CPC classification number: H01L24/29 ,  B23K35/0233 ,  B23K35/26 ,  B23K35/262 ,  C22C13/00 ,  H01L21/52 ,  H01L23/00 ,  H01L23/488 ,  H01L2224/29083 ,  H01L2224/29209 ,  H01L2224/29211 ,  H01L2224/29213 ,  H01L2224/29217 ,  H01L2224/29239 ,  H01L2224/29247 ,  H01L2224/29255 ,  H01L2224/29257 ,  H01L2924/014 ,  H01L2924/3512

Abstract: A mount structure includes two members that are bonded to each other with a bonding material layer having a first interface layer and a second interface layer at the interfaces with the two members. The bonding material layer contains a first intermetallic compound and a stress relaxation material. The first intermetallic compound has a spherical, a columnar, or an oval spherical shape, and the same crystalline structure as the first interface layer and the second interface layer, and partly closes the space between the first interface layer and the second interface layer. The stress relaxation material contains tin as a main component, and fills around the first intermetallic compound.

公开(公告)号：US20170229415A1

公开(公告)日：2017-08-10

申请号：US15427466

申请日：2017-02-08

Applicant: Kabushiki Kaisha Toshiba

Inventor： Yuchen HSU ,  Daisuke HIRATSUKA

IPC: H01L23/00

CPC classification number: H01L24/29 ,  H01L24/27 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/26165 ,  H01L2224/2732 ,  H01L2224/29076 ,  H01L2224/29239 ,  H01L2224/29247 ,  H01L2224/29255 ,  H01L2224/2929 ,  H01L2224/29305 ,  H01L2224/29309 ,  H01L2224/29311 ,  H01L2224/29313 ,  H01L2224/29339 ,  H01L2224/29347 ,  H01L2224/29355 ,  H01L2224/29499 ,  H01L2224/3201 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/83054 ,  H01L2224/8309 ,  H01L2224/8314 ,  H01L2224/83192 ,  H01L2224/8321 ,  H01L2224/83815 ,  H01L2224/8384 ,  H01L2224/83905 ,  H01L2224/92247 ,  H01L2924/01083 ,  H01L2924/014 ,  H01L2924/01049 ,  H01L2924/01031 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: In a method of manufacturing a semiconductor device of one embodiment, support members and a film which is formed of a paste containing metal particles and surrounds the support members are provided above a surface of a base. Then a semiconductor element is provided above the support members and the film. Subsequently, the film is sintered to join the base and the semiconductor element. The support members are formed of a metal which melts at a temperature equal to or below a sintering temperature of the metal particles contained in the paste. The support members support the semiconductor element after the semiconductor element is provided above the support members and the film.

公开(公告)号：US20140234649A1

公开(公告)日：2014-08-21

申请号：US14348408

申请日：2012-09-21

Applicant: Robert Bosch GmbH

Inventor： Thomas Kalich ,  Frank Wetzl ,  Bernd Hohenberger ,  Rainer Holz ,  Christiane Frueh ,  Andreas Fix ,  Michael Guyenot ,  Andrea Feiock ,  Martin Rittner ,  Michael Guenther

IPC: B23K35/02 ,  B32B15/06 ,  B23K1/00 ,  B32B15/16

CPC classification number: B23K35/0238 ,  B23K1/0008 ,  B23K1/0016 ,  B32B15/06 ,  B32B15/16 ,  B32B2264/105 ,  C23C26/00 ,  C23C28/021 ,  C23C28/023 ,  H01L24/27 ,  H01L24/29 ,  H01L24/83 ,  H01L2224/27003 ,  H01L2224/271 ,  H01L2224/27334 ,  H01L2224/27505 ,  H01L2224/278 ,  H01L2224/27848 ,  H01L2224/29082 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/29113 ,  H01L2224/29118 ,  H01L2224/29139 ,  H01L2224/29147 ,  H01L2224/29209 ,  H01L2224/29211 ,  H01L2224/29213 ,  H01L2224/29218 ,  H01L2224/29239 ,  H01L2224/29247 ,  H01L2224/293 ,  H01L2224/29339 ,  H01L2224/29347 ,  H01L2224/29355 ,  H01L2224/29395 ,  H01L2224/32503 ,  H01L2224/83191 ,  H01L2224/83193 ,  H01L2224/832 ,  H01L2224/83203 ,  H01L2224/83815 ,  H01L2224/8382 ,  H01L2224/8384 ,  H01L2924/01327 ,  H01L2924/07811 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/351 ,  H05K3/3478 ,  H05K2203/0405 ,  H05K2203/1131 ,  Y10T428/12049 ,  Y10T428/12063 ,  H01L2924/00013 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01083 ,  H01L2924/01028 ,  H01L2924/0103 ,  H01L2924/01049 ,  H01L2924/01013 ,  H01L2924/01031 ,  H01L2924/0132 ,  H01L2924/00

Abstract: The invention relates to a layered composite (10), in particular for connecting electronic components as joining partners, comprising at least one substrate film (11) and a layer assembly (12) applied to the substrate film. The layer assembly comprises at least one sinterable layer (13), which is applied to the substrate film (11) and which contains at least one metal powder, and a solder layer (14) applied to the sinterable layer (13). The invention further relates to a method for forming a layered composite, to a circuit assembly containing a layered composite (10) according to the invention, and to the use of a layered composite (10) in a joining method for electronic components.

Abstract translation: 本发明涉及一种分层复合材料（10），特别是用于连接作为接合伙伴的电子部件，包括至少一个基底膜（11）和施加到基底膜上的层组件（12）。 层组件包括施加到基底膜（11）并且包含至少一种金属粉末的至少一个可烧结层（13）和施加到可烧结层（13）的焊料层（14）。 本发明还涉及一种用于形成层状复合材料的方法，包括根据本发明的层状复合材料（10）的电路组件，以及在电子部件的接合方法中使用层状复合材料（10）。

公开(公告)号：US11842968B2

公开(公告)日：2023-12-12

申请号：US17732751

申请日：2022-04-29

Applicant: MITSUBISHI ELECTRIC CORPORATION

Inventor： Kohei Yabuta ,  Takayuki Yamada ,  Yuya Muramatsu ,  Noriyuki Besshi ,  Yutaro Sugi ,  Hiroaki Haruna ,  Masaru Fuku ,  Atsuki Fujita

IPC: H01L23/00 ,  H01L21/48 ,  H01L23/13

CPC classification number: H01L23/562 ,  H01L21/4878 ,  H01L23/13 ,  H01L24/29 ,  H01L24/83 ,  H01L2224/29021 ,  H01L2224/29239 ,  H01L2224/29244 ,  H01L2224/29247 ,  H01L2224/29264 ,  H01L2224/29269 ,  H01L2224/8384 ,  H01L2924/1033 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/1203 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/35121

Abstract: A power semiconductor device includes a substrate and a semiconductor element bonded onto a first surface of the substrate through use of a sintered metal bonding material. The substrate has a plurality of dimples formed in the first surface and located outside a location immediately below a heat generation unit of the semiconductor element. The sintered metal bonding material is supplied onto the substrate after the formation of the dimples, and the semiconductor element is bonded to the substrate through application of heat and a pressure thereto.

公开(公告)号：US11801556B2

公开(公告)日：2023-10-31

申请号：US16978436

申请日：2019-02-15

Applicant: MITSUBISHI MATERIALS CORPORATION

Inventor： Tomohiko Yamaguchi ,  Koutarou Masuyama ,  Kazuhiko Yamasaki ,  Akihiro Higami

IPC: B23K35/00 ,  B22F9/24 ,  B23K35/02 ,  B23K35/30 ,  H01L23/00 ,  B22F1/16 ,  B22F1/054 ,  B22F1/107 ,  B22F1/10 ,  B22F1/148 ,  B22F1/052

CPC classification number: B22F9/24 ,  B22F1/052 ,  B22F1/054 ,  B22F1/056 ,  B22F1/10 ,  B22F1/107 ,  B22F1/148 ,  B22F1/16 ,  B23K35/025 ,  B23K35/302 ,  B23K35/3006 ,  H01L24/29 ,  H01L24/83 ,  B22F2301/10 ,  B22F2301/255 ,  B22F2302/45 ,  B22F2304/056 ,  B22F2304/058 ,  H01L2224/29239 ,  H01L2224/29247 ,  H01L2224/8384 ,  B22F2998/10 ,  B22F9/24 ,  B22F1/142 ,  B22F1/148 ,  B22F1/107 ,  B22F3/10 ,  B22F2007/047 ,  B22F2998/10 ,  B22F9/24 ,  B22F1/142 ,  B22F1/148 ,  B22F2998/10 ,  B22F9/24 ,  B22F1/142 ,  B22F1/148 ,  B22F1/107

Abstract: A metal particle aggregate includes metal particles and an organic substance. The metal particles include first particles that contain one or both of silver and copper in an amount of 70% by mass or more relative to 100% by mass of all metals and have a particle diameter of 100 nm or more and less than 500 nm at a ratio of 20 to 30% by number, and include second particles that have a particle diameter of 50 nm or more and less than 100 nm, and third particles that have a particle diameter of less than 50 nm at a ratio of 80 to 70% by number in total. Surfaces of the first to third particles are covered with the same protective film.