公开(公告)号：US09825165B2

公开(公告)日：2017-11-21

申请号：US14973385

申请日：2015-12-17

Applicant: Infineon Technologies Austria AG

Inventor： Hans Weber ,  Markus Schmitt ,  Andreas Voerckel

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/10

CPC classification number: H01L29/7811 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/4238 ,  H01L29/7813

Abstract: A charge-compensation semiconductor device includes a semiconductor body having a first surface, a lateral edge delimiting the semiconductor body in a horizontal direction substantially parallel to the first surface, an active area, a peripheral area arranged between the active area and the lateral edge, a drift region, first compensation regions forming respective first pn-junctions with the drift region, and second compensation regions extending from the first surface into the drift region and forming respective second pn-junctions with the drift region. The first compensation regions form in the active area a lattice comprising a first base vector having a first length. The second compensation regions have, in a horizontal direction parallel to the first surface, a horizontal width which decreases with an increasing vertical distance from the first surface and with a decreasing horizontal distance from the edge.

公开(公告)号：US20150021670A1

公开(公告)日：2015-01-22

申请号：US14081413

申请日：2013-11-15

Applicant: Infineon Technologies Austria AG

Inventor： Hans-Joachim Schulze ,  Franz-Josef Niedernostheide ,  Anton Mauder ,  Joachim Weyers ,  Franz Hirler ,  Markus Schmitt ,  Armin Willmeroth ,  Björn Fischer ,  Stefan Gamerith

IPC: H01L29/78

CPC classification number: H01L29/0634 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/404 ,  H01L29/66712 ,  H01L29/78 ,  H01L29/7811 ,  H01L29/7823

Abstract: A field-effect semiconductor device includes a semiconductor body having a first surface and an edge, an active area, and a peripheral area between the active area and the edge, a source metallization on the first surface and a drain metallization. In the active area, first conductivity type drift portions alternate with second conductivity type compensation regions. The drift portions contact the drain metallization and have a first maximum doping concentration. The compensation regions are in Ohmic contact with the source metallization. The peripheral area includes a first edge termination region and a second semiconductor region in Ohmic contact with the drift portions having a second maximum doping of the first conductivity type which lower than the first maximum doping concentration by a factor of ten. The first edge termination region of the second conductivity type adjoins the second semiconductor region and is in Ohmic contact with the source metallization.

Abstract translation: 场效应半导体器件包括具有第一表面和边缘的半导体本体，有源区域和有源区域与边缘之间的周边区域，第一表面上的源极金属化和漏极金属化。 在有源区域中，第一导电型漂移部分与第二导电类型补偿区域交替。 漂移部分接触漏极金属化并具有第一最大掺杂浓度。 补偿区域与源极金属化处于欧姆接触状态。 外围区域包括第一边缘终止区域和与漂移部分欧姆接触的第二半导体区域，其具有比第一最大掺杂浓度低十倍的第一导电类型的第二最大掺杂。 第二导电类型的第一边缘端接区域与第二半导体区域相邻并与源极金属化处于欧姆接触。

公开(公告)号：US20140327104A1

公开(公告)日：2014-11-06

申请号：US13874898

申请日：2013-05-01

Applicant: Infineon Technologies Austria AG

Inventor： Armin Willmeroth ,  Stefan Gamerith ,  Markus Schmitt ,  Bjoern Fischer

IPC: H01L29/06

CPC classification number: H01L29/0634 ,  H01L21/26586 ,  H01L29/0649 ,  H01L29/7395 ,  H01L29/7802 ,  H01L29/7813 ,  H01L29/861

Abstract: A super junction semiconductor device includes a layered compensation structure with an n-type compensation layer and a p-type compensation layer, a dielectric layer facing the p-type layer, and an intermediate layer interposed between the dielectric layer and the p-type compensation layer. The layered compensation structure and the intermediate layer are provided such that when a reverse blocking voltage is applied between the n-type and p-type compensation layers, holes accelerated in the direction of the dielectric layer have insufficient energy to be absorbed and incorporated into the dielectric material. Since the dielectric layer absorbs and incorporates significantly less holes than without the intermediate layer, the breakdown voltage remains stable over a long operation time.

Abstract translation: 超结半导体器件包括具有n型补偿层和p型补偿层的层状补偿结构，与p型层相对的电介质层以及介于介电层和p型补偿之间的中间层 层。 提供分层补偿结构和中间层，使得当在n型和p型补偿层之间施加反向阻断电压时，在电介质层的方向上加速的空穴具有不足的能量被吸收并被并入 介电材料。 由于介电层吸收和结合比没有中间层明显更少的孔，所以击穿电压在长的操作时间内保持稳定。

公开(公告)号：US20140327069A1

公开(公告)日：2014-11-06

申请号：US13874895

申请日：2013-05-01

Applicant: Infineon Technologies Austria AG

Inventor： Armin Willmeroth ,  Markus Schmitt ,  Winfried Kaindl ,  Hans Weber

IPC: H01L29/10 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L29/105 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/7396 ,  H01L29/7397 ,  H01L29/7802 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/861

Abstract: A super junction structure is formed in a semiconductor portion of a super junction semiconductor device. The super junction structure includes a compensation structure with a first compensation layer of a first conductivity type and a second compensation layer of a complementary second conductivity type. The compensation structure lines at least sidewall portions of compensation trenches that extend between semiconductor mesas along a vertical direction perpendicular to a first surface of the semiconductor portion. Within the super junction structure and a pedestal layer that may adjoin the super junction structure, a sign of a lateral compensation rate changes along the vertical direction resulting in a local peak of a vertical electric field gradient and to improved avalanche ruggedness.

Abstract translation: 在超结半导体器件的半导体部分中形成超结结构。 超结结构包括具有第一导电类型的第一补偿层和互补第二导电类型的第二补偿层的补偿结构。 补偿结构至少在补偿沟槽的侧壁部分之间沿垂直于半导体部分的第一表面的垂直方向在半导体台面之间延伸。 在超结结构内部和可以与超结结构邻接的基座层，横向补偿速率的符号沿着垂直方向变化，导致垂直电场梯度的局部峰值和改善的雪崩坚固性。

公开(公告)号：US20140124851A1

公开(公告)日：2014-05-08

申请号：US13672185

申请日：2012-11-08

Applicant: Infineon Technologies Austria AG

Inventor： Stefan Gamerith ,  Markus Schmitt ,  Winfried Kaindl ,  Gerald Sölkner

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66712 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/66727 ,  H01L29/7802

Abstract: According to an embodiment, a method of forming a power semiconductor device is provided. The method includes providing a semiconductor substrate and forming an epitaxial layer on the semiconductor substrate. The epitaxial layer includes a body region, a source region, and a drift region. The method further includes forming a dielectric layer on the epitaxial layer. The dielectric layer is formed thicker above a drift region of the epitaxial layer than above at least part of the body region and the dielectric layer is formed at a temperature less than 950° C.

Abstract translation: 根据实施例，提供了一种形成功率半导体器件的方法。 该方法包括提供半导体衬底并在半导体衬底上形成外延层。 外延层包括体区，源极区和漂移区。 该方法还包括在外延层上形成电介质层。 电介质层在外延层的漂移区以上形成在上面至少部分体区，并且电介质层在低于950℃的温度下形成。

公开(公告)号：US20230197674A1

公开(公告)日：2023-06-22

申请号：US18111328

申请日：2023-02-17

Applicant: Infineon Technologies Austria AG

Inventor： Victor Verdugo ,  Katrin Schmidt ,  Steffen Schmidt ,  Markus Schmitt

IPC: H01L23/00 ,  B23K1/00 ,  H01L29/417 ,  H01L29/45 ,  H01L29/51

CPC classification number: H01L24/83 ,  B23K1/0016 ,  H01L24/29 ,  H01L24/32 ,  H01L29/41741 ,  H01L29/456 ,  H01L29/51 ,  B23K2101/40

Abstract: A semiconductor assembly includes a substrate including a metal die attach surface, a semiconductor die that is arranged on the substrate, the semiconductor die being configured as a power semiconductor device and comprising a semiconductor body, a rear side metallization, and a front side layer stack, the front side layer stack comprising a front side metallization and a contaminant protection layer that is between the front side metallization and the semiconductor body, and a diffusion soldered joint between the metal die attach surface and the rear side metallization, the diffusion soldered joint comprising one or more intermetallic phases throughout the diffusion soldered joint, wherein the contaminant protection layer is configured to prevent transmission of contaminants into the semiconductor body.

公开(公告)号：US10374056B2

公开(公告)日：2019-08-06

申请号：US15337829

申请日：2016-10-28

Applicant: Infineon Technologies Austria AG

Inventor： Katarzyna Kowalik-Seidl ,  Bjoern Fischer ,  Winfried Kaindl ,  Markus Schmitt ,  Matthias Wegscheider

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/265 ,  H01L29/06 ,  H01L29/739 ,  H01L29/08 ,  H01L29/10 ,  H01L21/225

Abstract: Disclosed is a method for producing a transistor device and a transistor device. The method includes: forming a source region of a first doping type in a body region of a second doping type in a semiconductor body; and forming a low-resistance region of the second doping type adjoining the source region in the body region. Forming the source region includes implanting dopant particles of the first doping type using an implantation mask via a first surface of the semiconductor body into the body region. Implanting the doping particles of the first doping type includes a tilted implantation.

公开(公告)号：US10256325B2

公开(公告)日：2019-04-09

申请号：US13672185

申请日：2012-11-08

Applicant: Infineon Technologies Austria AG

Inventor： Stefan Gamerith ,  Markus Schmitt ,  Winfried Kaindl ,  Gerald Sölkner

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/10

Abstract: According to an embodiment, a method of forming a power semiconductor device is provided. The method includes providing a semiconductor substrate and forming an epitaxial layer on the semiconductor substrate. The epitaxial layer includes a body region, a source region, and a drift region. The method further includes forming a dielectric layer on the epitaxial layer. The dielectric layer is formed thicker above a drift region of the epitaxial layer than above at least part of the body region and the dielectric layer is formed at a temperature less than 950° C.

公开(公告)号：US09209292B2

公开(公告)日：2015-12-08

申请号：US14081413

申请日：2013-11-15

Applicant: Infineon Technologies Austria AG

Inventor： Hans-Joachim Schulze ,  Franz-Josef Niedernostheide ,  Anton Mauder ,  Joachim Weyers ,  Franz Hirler ,  Markus Schmitt ,  Armin Willmeroth ,  Björn Fischer ,  Stefan Gamerith

IPC: H01L29/76 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/10

CPC classification number: H01L29/0634 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/404 ,  H01L29/66712 ,  H01L29/78 ,  H01L29/7811 ,  H01L29/7823

Abstract: A field-effect semiconductor device includes a semiconductor body having a first surface and an edge, an active area, and a peripheral area between the active area and the edge, a source metallization on the first surface and a drain metallization. In the active area, first conductivity type drift portions alternate with second conductivity type compensation regions. The drift portions contact the drain metallization and have a first maximum doping concentration. The compensation regions are in Ohmic contact with the source metallization. The peripheral area includes a first edge termination region and a second semiconductor region in Ohmic contact with the drift portions having a second maximum doping of the first conductivity type which lower than the first maximum doping concentration by a factor of ten. The first edge termination region of the second conductivity type adjoins the second semiconductor region and is in Ohmic contact with the source metallization.

Abstract translation: 场效应半导体器件包括具有第一表面和边缘的半导体本体，有源区域和有源区域与边缘之间的周边区域，第一表面上的源极金属化和漏极金属化。 在有源区域中，第一导电型漂移部分与第二导电类型补偿区域交替。 漂移部分接触漏极金属化并具有第一最大掺杂浓度。 补偿区域与源极金属化处于欧姆接触状态。 外围区域包括第一边缘终止区域和与漂移部分欧姆接触的第二半导体区域，其具有比第一最大掺杂浓度低十倍的第一导电类型的第二最大掺杂。 第二导电类型的第一边缘端接区域与第二半导体区域相邻并与源极金属化处于欧姆接触。

公开(公告)号：US09070580B2

公开(公告)日：2015-06-30

申请号：US13874895

申请日：2013-05-01

Applicant: Infineon Technologies Austria AG

Inventor： Armin Willmeroth ,  Markus Schmitt ,  Winfried Kaindl ,  Hans Weber

IPC: H01L29/66 ,  H01L29/10 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L29/105 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/7396 ,  H01L29/7397 ,  H01L29/7802 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/861

Abstract: A super junction structure is formed in a semiconductor portion of a super junction semiconductor device. The super junction structure includes a compensation structure with a first compensation layer of a first conductivity type and a second compensation layer of a complementary second conductivity type. The compensation structure lines at least sidewall portions of compensation trenches that extend between semiconductor mesas along a vertical direction perpendicular to a first surface of the semiconductor portion. Within the super junction structure and a pedestal layer that may adjoin the super junction structure, a sign of a lateral compensation rate changes along the vertical direction resulting in a local peak of a vertical electric field gradient and to improved avalanche ruggedness.

Abstract translation: 在超结半导体器件的半导体部分中形成超结结构。 超结结构包括具有第一导电类型的第一补偿层和互补第二导电类型的第二补偿层的补偿结构。 补偿结构至少在补偿沟槽的侧壁部分之间沿垂直于半导体部分的第一表面的垂直方向在半导体台面之间延伸。 在超结结构内部和可以与超结结构邻接的基座层，横向补偿速率的符号沿着垂直方向变化，导致垂直电场梯度的局部峰值和改善的雪崩坚固性。