公开(公告)号：US20230344422A1

公开(公告)日：2023-10-26

申请号：US18130502

申请日：2023-04-04

Applicant: Infineon Technologies Austria AG

Inventor： Christian Fachmann ,  Matteo-Alessandro Kutschak ,  Otto Wiedenbauer ,  Winfried Kaindl ,  Hans Weber

IPC: H03K17/0812 ,  H03K17/284

CPC classification number: H03K17/08122 ,  H03K17/284

Abstract: A method is disclosed. The method includes switching off a power transistor circuit in an electronic circuit. The electronic circuit includes a power source and a load circuit. The power transistor circuit is connected between the power source and the load circuit. Switching off the power transistor circuit includes operating at least one power transistor included in the power transistor circuit in an Avalanche mode so that at least a portion of energy stored in the electronic circuit before switching off the power transistor circuit is dissipated in the at least one power transistor.

公开(公告)号：US10943987B2

公开(公告)日：2021-03-09

申请号：US16452070

申请日：2019-06-25

Applicant: Infineon Technologies Austria AG

Inventor： Katarzyna Kowalik-Seidl ,  Bjoern Fischer ,  Winfried Kaindl ,  Markus Schmitt ,  Matthias Wegscheider

IPC: H01L21/265 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L29/739 ,  H01L29/417 ,  H01L29/08 ,  H01L29/10 ,  H01L21/225

Abstract: A transistor device includes at least one transistor cell, having, in a semiconductor body, a source region of a first doping type in a body region of a second doping type, a drain region, and a drift region of the first doping type adjoining the body region and arranged between the body region and the drain region. A low-resistance region of the second doping type in the body region adjoins the source region. A gate electrode dielectrically insulated from the source and body regions by a gate dielectric is arranged above a first surface of the semiconductor body. A length of an overlap between the source region and the gate electrode is larger than 70 nanometers. A doping profile of the low-resistance region along a line that is vertical to the first surface and goes through an edge of the gate electrode has a maximum of higher than 1E19 cm−3.

公开(公告)号：US20190319110A1

公开(公告)日：2019-10-17

申请号：US16452070

申请日：2019-06-25

Applicant: Infineon Technologies Austria AG

Inventor： Katarzyna Kowalik-Seidl ,  Bjoern Fischer ,  Winfried Kaindl ,  Markus Schmitt ,  Matthias Wegscheider

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/739 ,  H01L29/417 ,  H01L29/06 ,  H01L21/265

Abstract: A transistor device includes at least one transistor cell, having, in a semiconductor body, a source region of a first doping type in a body region of a second doping type, a drain region, and a drift region of the first doping type adjoining the body region and arranged between the body region and the drain region. A low-resistance region of the second doping type in the body region adjoins the source region. A gate electrode dielectrically insulated from the source and body regions by a gate dielectric is arranged above a first surface of the semiconductor body. A length of an overlap between the source region and the gate electrode is larger than 70 nanometers. A doping profile of the low-resistance region along a line that is vertical to the first surface and goes through an edge of the gate electrode has a maximum of higher than 1E19 cm−3.

公开(公告)号：US09899510B2

公开(公告)日：2018-02-20

申请号：US15349595

申请日：2016-11-11

Applicant: Infineon Technologies Austria AG

Inventor： Winfried Kaindl ,  Franz Hirler ,  Armin Willmeroth

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/08 ,  H01L29/10 ,  H01L29/49

CPC classification number: H01L29/7813 ,  H01L27/088 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/4238 ,  H01L29/4916 ,  H01L29/7802

Abstract: The present disclosure provides a semiconductor device, which includes a compensation area which includes p-regions and n-regions, and a plurality of transistor cells on the compensation area. Each of the plurality of transistor cells includes a source region, a body region, a gate and an interlayer dielectric, and a source metallization layer arranged on the interlayer dielectric. The semiconductor device further includes an additional n-doping region that is provided on top of the n-regions between two neighboring body regions, and a source plug which fills a contact hole formed through the interlayer dielectric between the source and body region and the source metallization layer, so as to electrically connect the source and body region and the source metallization layer.

公开(公告)号：US11374125B2

公开(公告)日：2022-06-28

申请号：US16823510

申请日：2020-03-19

Applicant: Infineon Technologies Austria AG

Inventor： Winfried Kaindl ,  Gabor Mezoesi ,  Enrique Vecino Vazquez

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423

Abstract: A transistor device includes transistor cells each having source and drift regions of a first doping type and a body region of a second doping type in a first region of a semiconductor body, and a gate electrode dielectrically insulated from the body region. A gate conductor arranged on top of a second region of the semiconductor body is electrically connected to each gate electrode. A source conductor arranged on top of the first region is connected to each source and body region. A discharging region of the second doping type is arranged in the second region and located at least partially below the gate conductor, and includes at least one lower dose section in which a doping dose is lower than a minimum doping dose in other sections of the discharging region. The at least one lower dose section is associated with a corner of the gate conductor.

公开(公告)号：US09524966B2

公开(公告)日：2016-12-20

申请号：US14527831

申请日：2014-10-30

Applicant: Infineon Technologies Austria AG

Inventor： Winfried Kaindl ,  Franz Hirler ,  Armin Willmeroth

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L29/7813 ,  H01L27/088 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/4238 ,  H01L29/4916 ,  H01L29/7802

Abstract: The present disclosure provides a semiconductor device, which includes a compensation area which includes p-regions and n-regions, and a plurality of transistor cells on the compensation area. Each of the plurality of transistor cells includes a source region, a body region, a gate and an interlayer dielectric, and a source metallization layer arranged on the interlayer dielectric. The semiconductor device further includes an additional n-doping region that is provided on top of the n-regions between two neighboring body regions, and a source plug which fills a contact hole formed through the interlayer dielectric between the source and body region and the source metallization layer, so as to electrically connect the source and body region and the source metallization layer.

Abstract translation: 本公开提供了一种半导体器件，其包括包括p区和n区的补偿区和在补偿区上的多个晶体管单元。 多个晶体管单元中的每一个包括源极区域，体区域，栅极和层间电介质，以及布置在层间电介质上的源极金属化层。 半导体器件还包括设置在两个相邻体区之间的n区的顶部的附加n掺杂区，以及填充通过源极和体区之间的层间电介质形成的接触孔的源极和源 金属化层，以便电源和源区域和源金属化层电连接。

公开(公告)号：US20150115358A1

公开(公告)日：2015-04-30

申请号：US14525312

申请日：2014-10-28

Applicant: Infineon Technologies Austria AG

Inventor： Anton Mauder ,  Winfried Kaindl ,  Uwe Wahl

IPC: H01L27/088 ,  H01L29/423 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L29/06 ,  H01L29/49

CPC classification number: H01L29/4916 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/7802 ,  H01L29/7813

Abstract: The present disclosure provides a semiconductor device, including a compensation area that includes p-regions and n-regions, a plurality of transistor cells including gate electrodes on the compensation area, and one or more interconnections for electrically connecting gate electrodes. The gate electrodes may have a width smaller than ½ of a pitch of the cells.

Abstract translation: 本公开提供一种半导体器件，包括包括p区和n区的补偿区，在补偿区上包括栅极的多个晶体管单元和用于电连接栅电极的一个或多个互连。 栅电极可以具有小于单元间距的1/2的宽度。

公开(公告)号：US20150115354A1

公开(公告)日：2015-04-30

申请号：US14527831

申请日：2014-10-30

Applicant: Infineon Technologies Austria AG

Inventor： Winfried Kaindl ,  Franz Hirler ,  Armin Willmeroth

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/45 ,  H01L29/49 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L29/7813 ,  H01L27/088 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/4238 ,  H01L29/4916 ,  H01L29/7802

Abstract: The present disclosure provides a semiconductor device, which includes a compensation area which includes p-regions and n-regions, and a plurality of transistor cells on the compensation area. Each of the plurality of transistor cells includes a source region, a body region, a gate and an interlayer dielectric, and a source metallization layer arranged on the interlayer dielectric. The semiconductor device further includes an additional n-doping region that is provided on top of the n-regions between two neighboring body regions, and a source plug which fills a contact hole formed through the interlayer dielectric between the source and body region and the source metallization layer, so as to electrically connect the source and body region and the source metallization layer.

Abstract translation: 本公开提供了一种半导体器件，其包括包括p区和n区的补偿区和在补偿区上的多个晶体管单元。 多个晶体管单元中的每一个包括源极区域，体区域，栅极和层间电介质，以及布置在层间电介质上的源极金属化层。 半导体器件还包括设置在两个相邻体区之间的n区的顶部的附加n掺杂区，以及填充通过源极和体区之间的层间电介质形成的接触孔的源极和源 金属化层，以便电源和源区域和源金属化层电连接。

公开(公告)号：US11869966B2

公开(公告)日：2024-01-09

申请号：US17528313

申请日：2021-11-17

Applicant: Infineon Technologies Austria AG

Inventor： Hans Weber ,  Christian Fachmann ,  Franz Hirler ,  Winfried Kaindl ,  Markus Rochel

IPC: H01L29/78 ,  H01L21/265 ,  H01L21/3105 ,  H01L21/762 ,  H01L21/765 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/40

CPC classification number: H01L29/7802 ,  H01L21/265 ,  H01L21/31053 ,  H01L21/765 ,  H01L21/76224 ,  H01L21/823487 ,  H01L29/0634 ,  H01L29/402

Abstract: A method includes forming a trench in a first surface in an edge region of a semiconductor body, forming a plurality of superjunction transistor cells in an inner region of a semiconductor body, and forming an insulation layer on the first surface of the semiconductor body in the edge region and in the inner region, wherein forming the insulation layer includes a thermal oxidation process.

公开(公告)号：US10374056B2

公开(公告)日：2019-08-06

申请号：US15337829

申请日：2016-10-28

Applicant: Infineon Technologies Austria AG

Inventor： Katarzyna Kowalik-Seidl ,  Bjoern Fischer ,  Winfried Kaindl ,  Markus Schmitt ,  Matthias Wegscheider

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/265 ,  H01L29/06 ,  H01L29/739 ,  H01L29/08 ,  H01L29/10 ,  H01L21/225

Abstract: Disclosed is a method for producing a transistor device and a transistor device. The method includes: forming a source region of a first doping type in a body region of a second doping type in a semiconductor body; and forming a low-resistance region of the second doping type adjoining the source region in the body region. Forming the source region includes implanting dopant particles of the first doping type using an implantation mask via a first surface of the semiconductor body into the body region. Implanting the doping particles of the first doping type includes a tilted implantation.