知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

5 records (took 0.046 seconds)

    Latch-Up Resistant Transistor Device
    4.
    发明申请
    Latch-Up Resistant Transistor Device 审中-公开

    公开(公告)号：US20190319110A1

    公开(公告)日：2019-10-17

    申请号：US16452070

    申请日：2019-06-25

    Applicant: Infineon Technologies Austria AG

    Inventor： Katarzyna Kowalik-Seidl ,  Bjoern Fischer ,  Winfried Kaindl ,  Markus Schmitt ,  Matthias Wegscheider

    IPC: H01L29/66 ,  H01L29/78 ,  H01L29/739 ,  H01L29/417 ,  H01L29/06 ,  H01L21/265

    Abstract: A transistor device includes at least one transistor cell, having, in a semiconductor body, a source region of a first doping type in a body region of a second doping type, a drain region, and a drift region of the first doping type adjoining the body region and arranged between the body region and the drain region. A low-resistance region of the second doping type in the body region adjoins the source region. A gate electrode dielectrically insulated from the source and body regions by a gate dielectric is arranged above a first surface of the semiconductor body. A length of an overlap between the source region and the gate electrode is larger than 70 nanometers. A doping profile of the low-resistance region along a line that is vertical to the first surface and goes through an edge of the gate electrode has a maximum of higher than 1E19 cm−3.

    TRANSISTOR MODEL, A METHOD FOR A COMPUTER BASED DETERMINATION OF CHARACTERISTIC OF A TRANSISTOR, A DEVICE AND A COMPUTER READABLE STORAGE MEDIUM FOR PERFORMING THE METHOD
    5.
    发明申请
    TRANSISTOR MODEL, A METHOD FOR A COMPUTER BASED DETERMINATION OF CHARACTERISTIC OF A TRANSISTOR, A DEVICE AND A COMPUTER READABLE STORAGE MEDIUM FOR PERFORMING THE METHOD 审中-公开

    公开(公告)号：US20170242949A1

    公开(公告)日：2017-08-24

    申请号：US15431841

    申请日：2017-02-14

    Applicant: INFINEON TECHNOLOGIES AUSTRIA AG

    Inventor： Patrick Schindler ,  Katarzyna Kowalik-Seidl ,  Franz Hirler

    IPC: G06F17/50

    CPC classification number: G06F17/5036 ,  H01L29/0634 ,  H01L29/7802 ,  H01L29/7804 ,  H01L29/7805

    Abstract: According to various embodiments, a transistor model for a computer based simulation of a field effect transistor may include: a first electrical network coupled between a drain node, a source node and a gate node, wherein the first electrical network is configured to represent an electrical characteristic of the field effect transistor in a forward operation; a second electrical network coupled parallel to the first electrical network and between the source node and the drain node, wherein the second electrical network is configured to represent an electrical characteristic of the field effect transistor in at least one of a commutation operation and a reverse operation; wherein the second electrical network includes: a controlled first source representing a parasitic junction of the field effect transistor; at least one controlled second source representing a charge injection dependent parasitic impedance of the field effect transistor; wherein the controlled first source and the at least one controlled second source are coupled in parallel; and wherein the controlled first source and the at least one controlled second source are coupled via at least one parameter such that a charge injection from the parasitic junction into the parasitic impedance is considered.

Patent Agency Ranking