公开(公告)号：US12079155B2

公开(公告)日：2024-09-03

申请号：US17428216

申请日：2020-03-14

Applicant: Intel Corporation

Inventor： Joydeep Ray ,  Selvakumar Panneer ,  Saurabh Tangri ,  Ben Ashbaugh ,  Scott Janus ,  Abhishek Appu ,  Varghese George ,  Ravishankar Iyer ,  Nilesh Jain ,  Pattabhiraman K ,  Altug Koker ,  Mike MacPherson ,  Josh Mastronarde ,  Elmoustapha Ould-Ahmed-Vall ,  Jayakrishna P. S ,  Eric Samson

IPC: G06F15/78 ,  G06F7/544 ,  G06F7/575 ,  G06F7/58 ,  G06F9/30 ,  G06F9/38 ,  G06F9/50 ,  G06F12/02 ,  G06F12/06 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0866 ,  G06F12/0871 ,  G06F12/0875 ,  G06F12/0882 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/128 ,  G06F15/80 ,  G06F17/16 ,  G06F17/18 ,  G06T1/20 ,  G06T1/60 ,  H03M7/46 ,  G06N3/08 ,  G06T15/06

CPC classification number: G06F15/7839 ,  G06F7/5443 ,  G06F7/575 ,  G06F7/588 ,  G06F9/3001 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/30065 ,  G06F9/30079 ,  G06F9/3887 ,  G06F9/5011 ,  G06F9/5077 ,  G06F12/0215 ,  G06F12/0238 ,  G06F12/0246 ,  G06F12/0607 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0866 ,  G06F12/0871 ,  G06F12/0875 ,  G06F12/0882 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/128 ,  G06F15/8046 ,  G06F17/16 ,  G06F17/18 ,  G06T1/20 ,  G06T1/60 ,  H03M7/46 ,  G06F9/3802 ,  G06F9/3818 ,  G06F9/3867 ,  G06F2212/1008 ,  G06F2212/1021 ,  G06F2212/1044 ,  G06F2212/302 ,  G06F2212/401 ,  G06F2212/455 ,  G06F2212/60 ,  G06N3/08 ,  G06T15/06

Abstract: Embodiments described herein include software, firmware, and hardware that provides techniques to enable deterministic scheduling across multiple general-purpose graphics processing units. One embodiment provides a multi-GPU architecture with uniform latency. One embodiment provides techniques to distribute memory output based on memory chip thermals. One embodiment provides techniques to enable thermally aware workload scheduling. One embodiment provides techniques to enable end to end contracts for workload scheduling on multiple GPUs.

公开(公告)号：US20240281171A1

公开(公告)日：2024-08-22

申请号：US18589184

申请日：2024-02-27

Applicant: Micron Technology, Inc.

Inventor： Dmitri A. Yudanov ,  Shanky Kumar Jain

IPC: G06F3/06 ,  G06F9/54 ,  G06F12/02 ,  G06F12/0802 ,  G06F12/0873 ,  G06F12/0875 ,  G06F12/0893 ,  G06F12/1045 ,  G11C7/08 ,  G11C7/10 ,  G11C8/08 ,  G11C11/22 ,  G11C11/406 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4096

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0673 ,  G06F9/546 ,  G06F12/0246 ,  G06F12/0802 ,  G06F12/0873 ,  G06F12/0875 ,  G06F12/0893 ,  G06F12/1045 ,  G11C7/08 ,  G11C7/1012 ,  G11C7/1063 ,  G11C7/109 ,  G11C8/08 ,  G11C11/221 ,  G11C11/2257 ,  G11C11/2259 ,  G11C11/2273 ,  G11C11/2275 ,  G11C11/2297 ,  G11C11/406 ,  G11C11/40603 ,  G11C11/4074 ,  G11C11/4085 ,  G11C11/4091 ,  G11C11/4096 ,  G06F2212/60 ,  G06F2212/608 ,  G06F2212/72 ,  G06F2212/7201

Abstract: Methods, systems, and devices related to write broadcast operations associated with a memory device are described. In one example, a memory device in accordance with the described techniques may include a memory array, a sense amplifier array, and a signal development cache configured to store signals (e.g., cache signals, signal states) associated with logic states (e.g., memory states) that may be stored at the memory array (e.g., according to various read or write operations). The memory device may enable read broadcast operations. A read broadcast may occur from the memory array to multiple locations of the signal development cache, for example via one or more multiplexers.

公开(公告)号：US12061909B2

公开(公告)日：2024-08-13

申请号：US18312380

申请日：2023-05-04

Applicant: International Business Machines Corporation

Inventor： Salma Ayub ,  Sundeep Chadha ,  Robert Allen Cordes ,  David Allen Hrusecky ,  Hung Qui Le ,  Dung Quoc Nguyen ,  Brian William Thompto

IPC: G06F9/38 ,  G06F9/30 ,  G06F12/0875

CPC classification number: G06F9/3802 ,  G06F9/30043 ,  G06F9/30145 ,  G06F9/3836 ,  G06F9/3885 ,  G06F12/0875 ,  G06F2212/1021 ,  G06F2212/452 ,  G06F2212/608

Abstract: An execution unit circuit for use in a processor core provides efficient use of area and energy by reducing the per-entry storage requirement of a load-store unit issue queue. The execution unit circuit includes a recirculation queue that stores the effective address of the load and store operations and the values to be stored by the store operations. A queue control logic controls the recirculation queue and issue queue so that that after the effective address of a load or store operation has been computed, the effective address of the load operation or the store operation is written to the recirculation queue and the operation is removed from the issue queue, so that address operands and other values that were in the issue queue entry no longer require storage. When a load or store operation is rejected by the cache unit, it is subsequently reissued from the recirculation queue.

公开(公告)号：US12061908B2

公开(公告)日：2024-08-13

申请号：US17472852

申请日：2021-09-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Joseph Zbiciak ,  Timothy Anderson

IPC: G06F9/32 ,  G06F9/30 ,  G06F9/345 ,  G06F9/38 ,  G06F11/00 ,  G06F12/02 ,  G06F12/0875 ,  G06F12/0897 ,  G06F13/16 ,  G06F13/40 ,  G06F11/10

CPC classification number: G06F9/321 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/30098 ,  G06F9/30112 ,  G06F9/30145 ,  G06F9/3016 ,  G06F9/32 ,  G06F9/345 ,  G06F9/3802 ,  G06F9/383 ,  G06F9/3867 ,  G06F11/00 ,  G06F12/0207 ,  G06F12/0875 ,  G06F12/0897 ,  G06F13/1605 ,  G06F13/4068 ,  G06F9/3836 ,  G06F11/10 ,  G06F2212/452 ,  G06F2212/60

Abstract: A streaming engine employed in a digital data processor specifies fixed first and second read only data streams. Corresponding stream address generator produces address of data elements of the two streams. Corresponding steam head registers stores data elements next to be supplied to functional units for use as operands. The two streams share two memory ports. A toggling preference of stream to port ensures fair allocation. The arbiters permit one stream to borrow the other's interface when the other interface is idle. Thus one stream may issue two memory requests, one from each memory port, if the other stream is idle. This spreads the bandwidth demand for each stream across both interfaces, ensuring neither interface becomes a bottleneck.

公开(公告)号：US12045614B2

公开(公告)日：2024-07-23

申请号：US17467550

申请日：2021-09-07

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Joseph Zbiciak

IPC: G06F9/30 ,  G06F9/32 ,  G06F9/345 ,  G06F9/38 ,  G06F11/00 ,  G06F11/10 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0875

CPC classification number: G06F9/30043 ,  G06F9/30014 ,  G06F9/30021 ,  G06F9/30036 ,  G06F9/30112 ,  G06F9/30145 ,  G06F9/3016 ,  G06F9/32 ,  G06F9/345 ,  G06F9/3802 ,  G06F9/383 ,  G06F9/3867 ,  G06F11/00 ,  G06F11/1064 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0875 ,  G06F9/30047 ,  G06F11/10 ,  G06F2212/452 ,  G06F2212/621

Abstract: A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces address of data elements. A steam head register stores data elements next to be supplied to functional units for use as operands. The streaming engine fetches stream data ahead of use by the central processing unit core in a stream buffer constructed like a cache. The stream buffer cache includes plural cache lines, each includes tag bits, at least one valid bit and data bits. Cache lines are allocated to store newly fetched stream data. Cache lines are deallocated upon consumption of the data by a central processing unit core functional unit. Instructions preferably include operand fields with a first subset of codings corresponding to registers, a stream read only operand coding and a stream read and advance operand coding.

公开(公告)号：US20240232082A1

公开(公告)日：2024-07-11

申请号：US18337052

申请日：2023-06-19

Applicant: SK hynix Inc.

Inventor： Seon Ju LEE ,  Geon Woo KIM

IPC: G06F12/0811 ,  G06F12/0875

CPC classification number: G06F12/0811 ,  G06F12/0875 ,  G06F2212/1016

Abstract: The present disclosure relates to a storage device that optimally maintains a size of debugging data. Disclosed is a memory controller, including a first interface may communicate with a first external device; a second interface may generate a signal for controlling an operation of a second external device; a first volatile memory buffer; and a processor may generate and store the telemetry log data in the first volatile memory buffer; move and store the telemetry log data stored in the first volatile memory buffer to a first non-volatile memory buffer, when a size of the telemetry log data stored in the first volatile memory buffer is greater than or equal to a threshold size; and set the threshold size based on at least one among a number of telemetry logs stored in the first volatile memory buffer and a rising momentum of the number of the telemetry logs.

公开(公告)号：US20240211411A1

公开(公告)日：2024-06-27

申请号：US18587416

申请日：2024-02-26

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mujibur Rahman ,  Timothy David Anderson ,  Soujanya Narnur

IPC: G06F12/1045 ,  G06F7/24 ,  G06F7/487 ,  G06F7/499 ,  G06F7/53 ,  G06F7/57 ,  G06F9/30 ,  G06F9/32 ,  G06F9/345 ,  G06F9/38 ,  G06F9/48 ,  G06F11/00 ,  G06F11/10 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/0897 ,  G06F12/1009 ,  G06F15/78 ,  G06F17/16 ,  H03H17/06

CPC classification number: G06F12/1045 ,  G06F7/24 ,  G06F7/487 ,  G06F7/4876 ,  G06F7/49915 ,  G06F7/53 ,  G06F7/57 ,  G06F9/3001 ,  G06F9/30014 ,  G06F9/30021 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30065 ,  G06F9/30072 ,  G06F9/30098 ,  G06F9/30112 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/3016 ,  G06F9/32 ,  G06F9/345 ,  G06F9/3802 ,  G06F9/3818 ,  G06F9/383 ,  G06F9/3836 ,  G06F9/3851 ,  G06F9/3856 ,  G06F9/3867 ,  G06F9/3887 ,  G06F9/48 ,  G06F11/00 ,  G06F11/1048 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/0897 ,  G06F12/1009 ,  G06F17/16 ,  H03H17/0664 ,  G06F9/30018 ,  G06F9/325 ,  G06F9/381 ,  G06F9/3822 ,  G06F11/10 ,  G06F15/7807 ,  G06F15/781 ,  G06F2212/452 ,  G06F2212/60 ,  G06F2212/602 ,  G06F2212/68

Abstract: A processor is provided that includes a first multiplication unit in a first data path of the processor, the first multiplication unit configured to perform single issue multiply instructions, and a second multiplication unit in the first data path, the second multiplication unit configured to perform single issue multiply instructions, wherein the first multiplication unit and the second multiplication unit are configured to execute respective single issue multiply instructions in parallel.

公开(公告)号：US20240211405A1

公开(公告)日：2024-06-27

申请号：US18504468

申请日：2023-11-08

Applicant: NXP USA, Inc.

Inventor： Rajan Srivastava ,  Sourav Roy

IPC: G06F12/0875 ,  G06F12/0811

CPC classification number: G06F12/0875 ,  G06F12/0811 ,  G06F2212/1021

Abstract: A system on chip (SoC) architecture includes an integrated branch and cache hit-miss trace circuit operably coupled to a CPU core, a first trace circuit, and a cache hit-miss trace circuit. Following an occurrence of a cache-fetch instruction: the cache hit-miss trace circuit identifies whether the fetch instruction is a cache-missed instruction, and, in response thereto, sends a cache miss report message that includes a fetch instruction address to the first trace circuit. The first trace circuit is configured to identify whether the fetch instruction is a taken-branch instruction and creates a modified branch trace response message (BTM) that includes the fetch instruction address and sends the modified BTM to a create trace messages circuit. The modified BTM indicates an instruction address of the cache miss.

公开(公告)号：US12019920B2

公开(公告)日：2024-06-25

申请号：US17958404

申请日：2022-10-02

Applicant: Micron Technology, Inc.

Inventor： Tony M. Brewer

IPC: G06F3/06 ,  G06F12/0875

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0683 ,  G06F12/0875 ,  G06F2212/452

Abstract: A memory controller circuit is disclosed which is coupleable to a first memory circuit, such as DRAM, and includes: a first memory control circuit to read from or write to the first memory circuit; a second memory circuit, such as SRAM; a second memory control circuit adapted to read from the second memory circuit in response to a read request when the requested data is stored in the second memory circuit, and otherwise to transfer the read request to the first memory control circuit; predetermined atomic operations circuitry; and programmable atomic operations circuitry adapted to perform at least one programmable atomic operation. The second memory control circuit also transfers a received programmable atomic operation request to the programmable atomic operations circuitry and sets a hazard bit for a cache line of the second memory circuit.

公开(公告)号：US20240202128A1

公开(公告)日：2024-06-20

申请号：US18288860

申请日：2022-03-07

Applicant: Hitachi, Ltd.

Inventor： Naushad SHAKOOR ,  Koichi OKITA ,  Yuta SEKIGUCHI

IPC: G06F12/0875

CPC classification number: G06F12/0875

Abstract: Data can be rapidly and flexibly converted. A data conversion apparatus stores monitoring target management information in which a monitoring target is associated with a controller type representing a type of a controller configured to control the monitoring target, and data conversion rule information in which a data set in units of the controller type is registered, the data set in units of the controller type defining a conversion rule indicating a data conversion method for the controller type. A calculation unit loads the data conversion rule information into the cache memory, specifies a monitoring target corresponding to data received from an edge device, specifies a controller type corresponding to the specified monitoring target by referring to the monitoring target management information, reads a conversion rule corresponding to the specified controller type from the cache memory, and converts the data using the conversion rule.