A system on chip (SoC) architecture includes an integrated branch and cache hit-miss trace circuit operably coupled to a CPU core, a first trace circuit, and a cache hit-miss trace circuit. Following an occurrence of a cache-fetch instruction: the cache hit-miss trace circuit identifies whether the fetch instruction is a cache-missed instruction, and, in response thereto, sends a cache miss report message that includes a fetch instruction address to the first trace circuit. The first trace circuit is configured to identify whether the fetch instruction is a taken-branch instruction and creates a modified branch trace response message (BTM) that includes the fetch instruction address and sends the modified BTM to a create trace messages circuit. The modified BTM indicates an instruction address of the cache miss.