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公开(公告)号：US12061909B2
公开(公告)日：2024-08-13
申请号：US18312380
申请日：2023-05-04
Applicant: International Business Machines Corporation
Inventor： Salma Ayub , Sundeep Chadha , Robert Allen Cordes , David Allen Hrusecky , Hung Qui Le , Dung Quoc Nguyen , Brian William Thompto
IPC: G06F9/38 , G06F9/30 , G06F12/0875
CPC classification number: G06F9/3802 , G06F9/30043 , G06F9/30145 , G06F9/3836 , G06F9/3885 , G06F12/0875 , G06F2212/1021 , G06F2212/452 , G06F2212/608
Abstract: An execution unit circuit for use in a processor core provides efficient use of area and energy by reducing the per-entry storage requirement of a load-store unit issue queue. The execution unit circuit includes a recirculation queue that stores the effective address of the load and store operations and the values to be stored by the store operations. A queue control logic controls the recirculation queue and issue queue so that that after the effective address of a load or store operation has been computed, the effective address of the load operation or the store operation is written to the recirculation queue and the operation is removed from the issue queue, so that address operands and other values that were in the issue queue entry no longer require storage. When a load or store operation is rejected by the cache unit, it is subsequently reissued from the recirculation queue.
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公开(公告)号：US11150907B2
公开(公告)日：2021-10-19
申请号：US16049038
申请日：2018-07-30
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Salma Ayub , Sundeep Chadha , Robert Allen Cordes , David Allen Hrusecky , Hung Qui Le , Dung Quoc Nguyen , Brian William Thompto
IPC: G06F9/38 , G06F9/30 , G06F12/0875
Abstract: An execution unit circuit for use in a processor core provides efficient use of area and energy by reducing the per-entry storage requirement of a load-store unit issue queue. The execution unit circuit includes a recirculation queue that stores the effective address of the load and store operations and the values to be stored by the store operations. A queue control logic controls the recirculation queue and issue queue so that that after the effective address of a load or store operation has been computed, the effective address of the load operation or the store operation is written to the recirculation queue and the operation is removed from the issue queue, so that address operands and other values that were in the issue queue entry no longer require storage. When a load or store operation is rejected by the cache unit, it is subsequently reissued from the recirculation queue.
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公开(公告)号：US11068267B2
公开(公告)日：2021-07-20
申请号：US16392722
申请日：2019-04-24
Applicant: International Business Machines Corporation
Inventor： Steven J. Battle , Brandon Goddard , Dung Q. Nguyen , Joshua W. Bowman , Brian D. Barrick , Susan Eisen , Salma Ayub , Christopher M. Mueller
Abstract: An aspect includes receiving a flush request at a processing unit that is in a current state defined by contents of registers in a register file. The processing unit includes a plurality of slices and the flush request includes an identifier of a previously issued instruction. The processing unit is restored to a previous state defined by contents of the registers in the register file prior to the previously issued instruction being issued. The restoring includes searching previous state buffers in at least two of the plurality of slices to locate data describing the contents of the registers in the register file prior to the previously issued instruction being issued. The restoring also includes combining the located data to generate results of the searching and updating the contents of the registers in the register file using a single port based at least in part on the results.
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公开(公告)号：US10445100B2
公开(公告)日：2019-10-15
申请号：US15177394
申请日：2016-06-09
Applicant: International Business Machines Corporation
Inventor： Salma Ayub , Joshua W. Bowman , Jeffrey C. Brownscheidle , Sundeep Chadha , Dhivya Jeganathan , Dung Q. Nguyen , Salim A. Shah , Brian W. Thompto
IPC: G06F9/38
Abstract: Methods and apparatus for transmitting data between execution slices of a multi-slice processor including receiving, by an execution slice, a broadcast message comprising an instruction tag (ITAG) for a producer instruction, a latency, and a source identifier; determining that an issue queue in the execution slice comprises an ITAG for a consumer instruction, wherein the consumer instruction depends on result data from the producer instruction; calculating a cycle countdown using the latency and the source identifier; determining that the cycle countdown has expired; and in response to determining that the cycle countdown has expired, reading the result data from the producer instruction.
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公开(公告)号：US12204902B2
公开(公告)日：2025-01-21
申请号：US17464227
申请日：2021-09-01
Applicant: International Business Machines Corporation
Inventor： Kurt A. Feiste , Brian W. Thompto , Susan E. Eisen , Salma Ayub , Dung Q. Nguyen
Abstract: A system, processor, programming product and/or method for assigning instructions to destination register file blocks, and/or routing instructions, includes: providing a processing pipeline having two or more execution units configured to process instructions; providing a register file having register file entries configured to hold data, where the register file is subdivided into a plurality of register blocks and each register block has two or more register file entries; calculating a utilization rate for one or more register blocks; and assigning and/or routing an instruction to write its results to a register block based upon the utilization rate for that register block. Preferably the execution unit is configured to write its results to a single specific destination (rename) register block.
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公开(公告)号：US11734010B2
公开(公告)日：2023-08-22
申请号：US17467882
申请日：2021-09-07
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Salma Ayub , Sundeep Chadha , Robert Allen Cordes , David Allen Hrusecky , Hung Qui Le , Dung Quoc Nguyen , Brian William Thompto
IPC: G06F9/38 , G06F9/30 , G06F12/0875
CPC classification number: G06F9/3802 , G06F9/30043 , G06F9/30145 , G06F9/3836 , G06F9/3885 , G06F12/0875 , G06F2212/1021 , G06F2212/452 , G06F2212/608
Abstract: An execution unit circuit for use in a processor core provides efficient use of area and energy by reducing the per-entry storage requirement of a load-store unit issue queue. The execution unit circuit includes a recirculation queue that stores the effective address of the load and store operations and the values to be stored by the store operations. A queue control logic controls the recirculation queue and issue queue so that that after the effective address of a load or store operation has been computed, the effective address of the load operation or the store operation is written to the recirculation queue and the operation is removed from the issue queue, so that address operands and other values that were in the issue queue entry no longer require storage. When a load or store operation is rejected by the cache unit, it is subsequently reissued from the recirculation queue.
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公开(公告)号：US11360779B2
公开(公告)日：2022-06-14
申请号：US17109583
申请日：2020-12-02
Applicant: International Business Machines Corporation
Inventor： Steven J. Battle , Salma Ayub , Brian D. Barrick , Joshua W. Bowman , Susan E. Eisen , Brandon Goddard , Christopher M. Mueller , Dung Q. Nguyen
Abstract: A computer system, processor, and method for processing information is disclosed that includes partitioning a logical register in the processor into a plurality of ranges of logical register entries based upon the logical register entry, assigning at least one recovery port of a history buffer to each range of logical register entries, initiating a flush recovery process for the processor, and directing history buffer entries to the assigned recovery port based upon the logical register entry associated with the history buffer entry.
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公开(公告)号：US11144319B1
公开(公告)日：2021-10-12
申请号：US16940433
申请日：2020-07-28
Applicant: International Business Machines Corporation
Inventor： Steven J. Battle , Susan E. Eisen , Dung Q. Nguyen , Salma Ayub , Albert J. Van Norstrand, Jr. , Kent Li , Kurt A. Feiste , Christian Gerhard Zoellin
Abstract: In an approach to dynamic redistribution of register files, whether a redistribution of register files is necessary is determined. Responsive to determining that the redistribution of register files is necessary, one or more register file transfers that have not yet completed are flushed. One or more register file write locations are allocated for each architected register based on a register free list. Source data is read from each architected register. The source data is written to the one or more register file write locations.
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公开(公告)号：US10740107B2
公开(公告)日：2020-08-11
申请号：US15170208
申请日：2016-06-01
Applicant: International Business Machines Corporation
Inventor： Salma Ayub , Joshua W. Bowman , Jeffrey C. Brownscheidle , Kurt A. Feiste , Dung Q. Nguyen , Salim A. Shah , Brian W. Thompto
Abstract: Operation of a multi-slice processor that includes a plurality of execution slices and an instruction sequencing unit. Operation of such a multi-slice processor includes: receiving, at the instruction sequencing unit, a load instruction indicating load address data and a load data length; determining a previous store instruction in an issue queue such that store address data for the previous store instruction corresponds to the load address data, wherein the previous store instruction corresponds to a store data length; and generating, in dependence upon the store data length matching the load data length, an indication in the issue queue that indicates a dependency between the load instruction and the previous store instruction.
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10.发明申请
公开(公告)号：US20180336036A1
公开(公告)日：2018-11-22
申请号：US16049038
申请日：2018-07-30
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Salma Ayub , Sundeep Chadha , Robert Allen Cordes , David Allen Hrusecky , Hung Qui Le , Dung Quoc Nguyen , Brian William Thompto
IPC: G06F9/38 , G06F12/0875 , G06F9/30
CPC classification number: G06F9/3802 , G06F9/30043 , G06F9/30145 , G06F9/3836 , G06F9/3885 , G06F12/0875 , G06F2212/1021 , G06F2212/452 , G06F2212/608
Abstract: An execution unit circuit for use in a processor core provides efficient use of area and energy by reducing the per-entry storage requirement of a load-store unit issue queue. The execution unit circuit includes a recirculation queue that stores the effective address of the load and store operations and the values to be stored by the store operations. A queue control logic controls the recirculation queue and issue queue so that that after the effective address of a load or store operation has been computed, the effective address of the load operation or the store operation is written to the recirculation queue and the operation is removed from the issue queue, so that address operands and other values that were in the issue queue entry no longer require storage. When a load or store operation is rejected by the cache unit, it is subsequently reissued from the recirculation queue.
