公开(公告)号：US20130249105A1

公开(公告)日：2013-09-26

申请号：US13426552

申请日：2012-03-21

Applicant: Yaojian Lin ,  Kang Chen

Inventor： Yaojian Lin ,  Kang Chen

IPC: H01L23/522 ,  H01L21/768

CPC classification number: H01L23/562 ,  H01L21/561 ,  H01L23/3157 ,  H01L23/5226 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L2224/02125 ,  H01L2224/02165 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05552 ,  H01L2224/05557 ,  H01L2224/05559 ,  H01L2224/05567 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/10126 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01082 ,  H01L2924/014

Abstract: A semiconductor device has a semiconductor die and first insulating layer formed over the semiconductor die. A plurality of first micro-vias can be formed in the first insulating layer. A conductive layer is formed in the first micro-openings and over the first insulating layer. A second insulating layer is formed over the first insulating layer and conductive layer. A portion of the second insulating layer is removed to expose the conductive layer and form a plurality of second micro-openings in the second insulating layer over the conductive layer. The second micro-openings can be micro-vias, micro-via ring, or micro-via slots. Removing the portion of the second insulating layer leaves an island of the second insulating layer over the conductive layer. A bump is formed over the conductive layer. A third insulating layer is formed in the second micro-openings over the bump. The second micro-openings provide stress relief.

Abstract translation: 半导体器件具有形成在半导体管芯上的半导体管芯和第一绝缘层。 可以在第一绝缘层中形成多个第一微通孔。 导电层形成在第一微孔中并在第一绝缘层之上。 在第一绝缘层和导电层上形成第二绝缘层。 去除第二绝缘层的一部分以暴露导电层并在导电层上的第二绝缘层中形成多个第二微孔。 第二微孔可以是微通孔，微通孔环或微通孔。 去除第二绝缘层的部分在导电层上留下第二绝缘层的岛。 在导电层上形成凸点。 在凸起上的第二微孔中形成第三绝缘层。 第二个微孔提供应力消除。

公开(公告)号：US08445323B2

公开(公告)日：2013-05-21

申请号：US13423739

申请日：2012-03-19

Applicant: Yaojian Lin ,  Jianmin Fang ,  Kang Chen ,  Haijing Cao

Inventor： Yaojian Lin ,  Jianmin Fang ,  Kang Chen ,  Haijing Cao

IPC: H01L21/00

CPC classification number: H01L25/0657 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/29 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0652 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/04042 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48463 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2924/00014 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19107 ,  H01L2924/30105 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A semiconductor device includes an IPD structure, a first semiconductor die mounted to the IPD structure with a flipchip interconnect, and a plurality of first conductive posts that are disposed adjacent to the first semiconductor die. The semiconductor device further includes a first molding compound that is disposed over the first conductive posts and first semiconductor die, a core structure bonded to the first conductive posts over the first semiconductor die, and a plurality of conductive TSVs disposed in the core structure. The semiconductor device further includes a plurality of second conductive posts that are disposed over the core structure, a second semiconductor die mounted over the core structure, and a second molding compound disposed over the second conductive posts and the second semiconductor die. The second semiconductor die is electrically connected to the core structure.

Abstract translation: 半导体器件包括IPD结构，安装到具有倒装芯片互连的IPD结构的第一半导体管芯和与第一半导体管芯相邻设置的多个第一导电柱。 半导体器件还包括设置在第一导电柱和第一半导体管芯之上的第一模塑料，与第一半导体管芯上的第一导电柱结合的芯结构以及设置在芯结构中的多个导电TSV。 半导体器件还包括设置在芯结构上的多个第二导电柱，安装在芯结构上的第二半导体管芯，以及设置在第二导电柱和第二半导体管芯上的第二模塑料。 第二半导体管芯与芯结构电连接。

公开(公告)号：US20130113092A9

公开(公告)日：2013-05-09

申请号：US13333739

申请日：2011-12-21

Applicant: Yaojian Lin ,  Pandi C. Marimuthu ,  Kang Chen ,  Hin Hwa Goh ,  Yu Gu ,  Il Kwon Shim ,  Rui Huang ,  Seng Guan Chow ,  Jianmin Fang ,  Xia Feng

Inventor： Yaojian Lin ,  Pandi C. Marimuthu ,  Kang Chen ,  Hin Hwa Goh ,  Yu Gu ,  Il Kwon Shim ,  Rui Huang ,  Seng Guan Chow ,  Jianmin Fang ,  Xia Feng

IPC: H01L23/52 ,  H01L21/56 ,  H01L21/78

CPC classification number: H01L23/3114 ,  H01L21/31 ,  H01L21/56 ,  H01L21/568 ,  H01L21/768 ,  H01L21/76877 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/522 ,  H01L23/528 ,  H01L23/5389 ,  H01L23/562 ,  H01L24/19 ,  H01L24/20 ,  H01L24/94 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/94 ,  H01L2224/96 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01043 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10156 ,  H01L2924/10157 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/3511 ,  H01L2224/19 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/03 ,  H01L2924/00012 ,  H01L2224/214

Abstract: A semiconductor device has a semiconductor die and conductive layer formed over a surface of the semiconductor die. A first channel can be formed in the semiconductor die. An encapsulant is deposited over the semiconductor die. A second channel can be formed in the encapsulant. A first insulating layer is formed over the semiconductor die and first conductive layer and into the first channel. The first insulating layer extends into the second channel. The first insulating layer has characteristics of tensile strength greater than 150 MPa, elongation between 35-150%, and thickness of 2-30 micrometers. A second insulating layer can be formed over the semiconductor die prior to forming the first insulating layer. An interconnect structure is formed over the semiconductor die and encapsulant. The interconnect structure is electrically connected to the first conductive layer. The first insulating layer provides stress relief during formation of the interconnect structure.

Abstract translation: 半导体器件具有形成在半导体管芯的表面上的半导体管芯和导电层。 可以在半导体管芯中形成第一通道。 密封剂沉积在半导体管芯上。 可以在密封剂中形成第二通道。 在半导体管芯和第一导电层上形成第一绝缘层并进入第一沟道。 第一绝缘层延伸到第二通道中。 第一绝缘层的拉伸强度大于150MPa，伸长率在35-150％之间，厚度为2-30微米。 在形成第一绝缘层之前，可以在半导体管芯上方形成第二绝缘层。 在半导体管芯和密封剂上形成互连结构。 互连结构电连接到第一导电层。 第一绝缘层在形成互连结构期间提供应力释放。

公开(公告)号：US08183087B2

公开(公告)日：2012-05-22

申请号：US12207332

申请日：2008-09-09

Applicant: Yaojian Lin ,  Jianmin Fang ,  Kang Chen ,  Haijing Cao

Inventor： Yaojian Lin ,  Jianmin Fang ,  Kang Chen ,  Haijing Cao

IPC: H01L21/00

CPC classification number: H01L21/565 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L24/48 ,  H01L2221/68372 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/1134 ,  H01L2224/16235 ,  H01L2224/20 ,  H01L2224/24195 ,  H01L2224/2518 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device is made by providing a temporary carrier for supporting the semiconductor device. An integrated passive device (IPD) is mounted to the temporary carrier using an adhesive. The IPD includes a capacitor and a resistor and has a plurality of through-silicon vias (TSVs). A discrete component is mounted to the temporary carrier using the adhesive. The discrete component includes a capacitor. The IPD and the discrete component are encapsulated using a molding compound. A first metal layer is formed over the molding compound. The first metal layer is connected to the TSVs of the IPD and forms an inductor. The temporary carrier and the adhesive are removed, and a second metal layer is formed over the IPD and the discrete component. The second metal layer interconnects the IPD and the discrete component and forms an inductor. An optional interconnect structure is formed over the second metal layer.

Abstract translation: 通过提供用于支撑半导体器件的临时载体来制造半导体器件。 使用粘合剂将集成无源器件（IPD）安装到临时载体上。 IPD包括电容器和电阻器，并且具有多个穿硅通孔（TSV）。 使用粘合剂将分立的部件安装到临时载体上。 分立元件包括电容器。 使用模塑料封装IPD和分立组件。 在模塑料上形成第一金属层。 第一金属层连接到IPD的TSV并形成电感器。 去除临时载体和粘合剂，并且在IPD和分立组件上形成第二金属层。 第二金属层将IPD和分立元件互连并形成电感器。 在第二金属层上形成可选的互连结构。

公开(公告)号：US20120018904A1

公开(公告)日：2012-01-26

申请号：US13181290

申请日：2011-07-12

Applicant: Yaojian Lin ,  Xia Feng ,  Jianmin Fang ,  Kang Chen

Inventor： Yaojian Lin ,  Xia Feng ,  Jianmin Fang ,  Kang Chen

IPC: H01L29/40 ,  H01L21/283

CPC classification number: H01L21/486 ,  H01L21/4857 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/48 ,  H01L23/525 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L2224/0231 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02317 ,  H01L2224/0235 ,  H01L2224/02379 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05548 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/06131 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16225 ,  H01L2224/29144 ,  H01L2224/2919 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48175 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73265 ,  H01L2924/00 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/381 ,  H05K2201/09854 ,  H01L2924/01014 ,  H01L2924/0665 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: A semiconductor device has a semiconductor die and first conductive layer formed over a surface of the semiconductor die. A first insulating layer is formed over the surface of the semiconductor die. A second insulating layer is formed over the first insulating layer and first conductive layer. An opening is formed in the second insulating layer over the first conductive layer. A second conductive layer is formed in the opening over the first conductive layer and second insulating layer. The second conductive layer has a width that is less than a width of the first conductive layer along a first axis. The second conductive layer has a width that is greater than a width of the first conductive layer along a second axis perpendicular to the first axis. A third insulating layer is formed over the second conductive layer and first insulating layer.

Abstract translation: 半导体器件具有形成在半导体管芯的表面上的半导体管芯和第一导电层。 在半导体管芯的表面上形成第一绝缘层。 在第一绝缘层和第一导电层上形成第二绝缘层。 在第一导电层上的第二绝缘层中形成开口。 在第一导电层和第二绝缘层上的开口中形成第二导电层。 第二导电层的宽度小于沿着第一轴线的第一导电层的宽度。 第二导电层的宽度大于沿着垂直于第一轴线的第二轴线的第一导电层的宽度。 在第二导电层和第一绝缘层上形成第三绝缘层。

公开(公告)号：US20110221055A1

公开(公告)日：2011-09-15

申请号：US12724367

申请日：2010-03-15

Applicant: Yaojian Lin ,  Kang Chen ,  Jianmin Fang ,  Xia Feng

Inventor： Yaojian Lin ,  Kang Chen ,  Jianmin Fang ,  Xia Feng

IPC: H01L23/48 ,  H01L21/78 ,  H01L21/60 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L21/76879 ,  H01L21/563 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/5226 ,  H01L23/5389 ,  H01L24/18 ,  H01L24/19 ,  H01L24/82 ,  H01L24/96 ,  H01L2223/5448 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/18 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01073 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10329 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor wafer has a plurality of first semiconductor die. A first conductive layer is formed over an active surface of the die. A first insulating layer is formed over the active surface and first conductive layer. A repassivation layer is formed over the first insulating layer and first conductive layer. A via is formed through the repassivation layer to the first conductive layer. The semiconductor wafer is singulated to separate the semiconductor die. The semiconductor die is mounted to a temporary carrier. An encapsulant is deposited over the semiconductor die and carrier. The carrier is removed. A second insulating layer is formed over the repassivation layer and encapsulant. A second conductive layer is formed over the repassivation layer and first conductive layer. A third insulating layer is formed over the second conductive layer and second insulating layer. An interconnect structure is formed over the second conductive layer.

Abstract translation: 半导体晶片具有多个第一半导体管芯。 在模具的有效表面上形成第一导电层。 在有源表面和第一导电层上形成第一绝缘层。 在第一绝缘层和第一导电层上形成再钝化层。 通过再钝化层形成通孔至第一导电层。 单个半导体晶片以分离半导体管芯。 半导体管芯安装在临时载体上。 密封剂沉积在半导体管芯和载体上。 载体被移除。 在再钝化层和密封剂上形成第二绝缘层。 在再钝化层和第一导电层上形成第二导电层。 在第二导电层和第二绝缘层上形成第三绝缘层。 在第二导电层上形成互连结构。

公开(公告)号：US20110127668A1

公开(公告)日：2011-06-02

申请号：US12628631

申请日：2009-12-01

Applicant: Yaojian Lin ,  Jianmin Fang ,  Kang Chen

Inventor： Yaojian Lin ,  Jianmin Fang ,  Kang Chen

IPC: H01L23/498 ,  H01L21/60 ,  H01L21/768

CPC classification number: H01L24/03 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/3185 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/13 ,  H01L24/14 ,  H01L24/29 ,  H01L24/48 ,  H01L2224/0231 ,  H01L2224/0233 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05082 ,  H01L2224/05111 ,  H01L2224/05155 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/1411 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/83805 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/10329 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2224/03 ,  H01L2924/00 ,  H01L2924/0665 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor wafer has a first conductive layer formed over its active surface. A first insulating layer is formed over the substrate and first conductive layer. A second conductive layer is formed over the first conductive layer and first insulating layer. A UBM layer is formed around a bump formation area over the second conductive layer. The UBM layer can be two stacked metal layers or three stacked metal layers. The second conductive layer is exposed in the bump formation area. A second insulating layer is formed over the UBM layer and second conductive layer. A portion of the second insulating layer is removed over the bump formation area and a portion of the UBM layer. A bump is formed over the second conductive layer in the bump formation area. The bump contacts the UBM layer to seal a contact interface between the bump and second conductive layer.

Abstract translation: 半导体晶片具有在其有效表面上形成的第一导电层。 第一绝缘层形成在衬底和第一导电层上。 在第一导电层和第一绝缘层上形成第二导电层。 在第二导电层上方的凸块形成区域周围形成UBM层。 UBM层可以是两个堆叠的金属层或三个堆叠的金属层。 第二导电层暴露在凸块形成区域中。 在UBM层和第二导电层上形成第二绝缘层。 第二绝缘层的一部分在凸块形成区域和UBM层的一部分上被去除。 在凸块形成区域中的第二导电层上形成凸块。 凸块接触UBM层以密封凸点和第二导电层之间的接触界面。

公开(公告)号：US07935570B2

公开(公告)日：2011-05-03

申请号：US12331698

申请日：2008-12-10

Applicant: Yaojian Lin ,  Jianmin Fang ,  Kang Chen ,  Haijing Cao

Inventor： Yaojian Lin ,  Jianmin Fang ,  Kang Chen ,  Haijing Cao

IPC: H01L21/00

CPC classification number: H01L23/3135 ,  H01L23/24 ,  H01L23/31 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/3157 ,  H01L23/5283 ,  H01L23/552 ,  H01L23/66 ,  H01L24/24 ,  H01L25/105 ,  H01L25/16 ,  H01L25/50 ,  H01L2223/6677 ,  H01L2224/04042 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/24195 ,  H01L2224/73265 ,  H01L2224/81005 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/30105 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A semiconductor device has a first insulation layer formed over a sacrificial substrate. A first conductive layer is formed over the first insulating layer. Conductive pillars are formed over the first conductive layer. A pre-fabricated IPD is disposed between the conductive pillars. An encapsulant is formed around the IPD and conductive pillars. A second insulation layer is formed over the encapsulant. The conductive pillars are electrically connected to the first and second conductive layers. The first and second conductive layers each include an inductor. Semiconductor devices are mounted over the first and second insulating layer and electrically connected to the first and second conductive layers, respectively. An interconnect structure is formed over the first and second insulating layers, respectively, and electrically connected to the first and second conductive layers. The sacrificial substrate is removed. The semiconductor devices can be stacked and electrically interconnected through the conductive pillars.

Abstract translation: 半导体器件具有形成在牺牲衬底上的第一绝缘层。 在第一绝缘层上形成第一导电层。 导电柱形成在第一导电层上。 预制IPD设置在导电柱之间。 在IPD和导电柱周围形成密封剂。 在密封剂上形成第二绝缘层。 导电柱电连接到第一和第二导电层。 第一和第二导电层各自包括电感器。 半导体器件安装在第一和第二绝缘层上，并分别电连接到第一和第二导电层。 互连结构分别形成在第一和第二绝缘层上，并且电连接到第一和第二导电层。 去除牺牲衬底。 半导体器件可以通过导电柱堆叠和电互连。

公开(公告)号：US20100059855A1

公开(公告)日：2010-03-11

申请号：US12207332

申请日：2008-09-09

Applicant: Yaojian Lin ,  Jianmin Fang ,  Kang Chen ,  Haijing Cao

Inventor： Yaojian Lin ,  Jianmin Fang ,  Kang Chen ,  Haijing Cao

IPC: H01L29/00 ,  H01L21/00

CPC classification number: H01L21/565 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L24/48 ,  H01L2221/68372 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/1134 ,  H01L2224/16235 ,  H01L2224/20 ,  H01L2224/24195 ,  H01L2224/2518 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device is made by providing a temporary carrier for supporting the semiconductor device. An integrated passive device (IPD) is mounted to the temporary carrier using an adhesive. The IPD includes a capacitor and a resistor and has a plurality of through-silicon vias (TSVs). A discrete component is mounted to the temporary carrier using the adhesive. The discrete component includes a capacitor. The IPD and the discrete component are encapsulated using a molding compound. A first metal layer is formed over the molding compound. The first metal layer is connected to the TSVs of the IPD and forms an inductor. The temporary carrier and the adhesive are removed, and a second metal layer is formed over the IPD and the discrete component. The second metal layer interconnects the IPD and the discrete component and forms an inductor. An optional interconnect structure is formed over the second metal layer.

Abstract translation: 通过提供用于支撑半导体器件的临时载体来制造半导体器件。 使用粘合剂将集成无源器件（IPD）安装到临时载体上。 IPD包括电容器和电阻器，并且具有多个穿硅通孔（TSV）。 使用粘合剂将分立的部件安装到临时载体上。 分立元件包括电容器。 使用模塑料封装IPD和分立组件。 在模塑料上形成第一金属层。 第一金属层连接到IPD的TSV并形成电感器。 去除临时载体和粘合剂，并且在IPD和分立组件上形成第二金属层。 第二金属层将IPD和分立元件互连并形成电感器。 在第二金属层上形成可选的互连结构。

公开(公告)号：US20090155959A1

公开(公告)日：2009-06-18

申请号：US11958603

申请日：2007-12-18

Applicant: Yaojian Lin ,  Haijing Cao ,  Qing Zhang ,  Kang Chen ,  Jianmin Fang

Inventor： Yaojian Lin ,  Haijing Cao ,  Qing Zhang ,  Kang Chen ,  Jianmin Fang

IPC: H01L21/50

CPC classification number: H01L23/50 ,  H01L21/4857 ,  H01L21/6835 ,  H01L23/3121 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/16 ,  H01L24/48 ,  H01L25/16 ,  H01L2221/68345 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19015 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K1/16 ,  H05K1/162 ,  H05K1/165 ,  H05K1/167 ,  H05K3/20 ,  H05K3/4602 ,  H05K2201/0352 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/09736 ,  H05K2203/016 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method of manufacturing a semiconductor device includes providing a substrate with an insulation layer disposed on a top surface of the substrate, forming a passive device over the top surface of the substrate, removing the substrate, depositing an insulating polymer film layer over the insulation layer, and depositing a metal layer over the insulating polymer film layer. A solder mask can be formed over the metal layer. A conformal metal layer can then be formed over the solder mask. A notch can be formed in the insulation layer to enhance the connection between the insulating polymer film layer and the insulation layer. Additional semiconductor die can be electrically connected to the passive device. The substrate is removed by removing a first amount of the substrate using a back grind process, and then removing a second amount of the substrate using a wet dry, dry etch, or chemical-mechanical planarization process.

Abstract translation: 一种制造半导体器件的方法包括：在衬底的顶表面上设置绝缘层，在衬底的顶表面上形成无源器件，去除衬底，在绝缘层上沉积绝缘聚合物膜层 并且在绝缘聚合物膜层上沉积金属层。 可以在金属层上形成焊接掩模。 然后可以在焊接掩模上形成保形金属层。 可以在绝缘层中形成切口以增强绝缘聚合物膜层和绝缘层之间的连接。 另外的半导体管芯可以电连接到无源器件。 通过使用后研磨工艺去除第一量的基材，然后使用湿干，干蚀刻或化学机械平面化工艺除去第二量的基材来除去基材。