公开(公告)号：US20240014180A1

公开(公告)日：2024-01-11

申请号：US18471326

申请日：2023-09-21

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Kuei Hsu ,  Feng-Cheng Hsu ,  Ming-Chih Yew ,  Po-Yao Lin ,  Shuo-Mao Chen ,  Shin-Puu Jeng

IPC: H01L25/065 ,  H01L21/50 ,  H01L21/768 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L21/50 ,  H01L21/768 ,  H01L23/31 ,  H01L23/5386 ,  H01L24/14 ,  H01L2224/0401

Abstract: A semiconductor package includes a semiconductor die, a redistribution circuit structure, a supporting structure and a protective layer. The redistribution circuit structure is located on and electrically coupled to the semiconductor die. The supporting structure is located on an outer surface of the redistribution circuit structure, wherein the supporting structure is overlapped with at least a part of the semiconductor die or has a sidewall substantially aligned with a sidewall of the semiconductor die in a vertical projection on the redistribution circuit structure along a stacking direction of the redistribution circuit structure and the supporting structure. The protective layer is located on the supporting structure, wherein the supporting structure is sandwiched between the protective layer and the redistribution circuit structure.

公开(公告)号：US20230352446A1

公开(公告)日：2023-11-02

申请号：US18347588

申请日：2023-07-06

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Feng-Cheng Hsu ,  Shin-Puu Jeng

IPC: H01L25/065 ,  H01L23/31 ,  H01L25/00 ,  H01L21/56 ,  H01L23/48 ,  H01L21/683 ,  H01L25/10

CPC classification number: H01L25/0652 ,  H01L23/3107 ,  H01L25/50 ,  H01L21/568 ,  H01L23/481 ,  H01L21/6835 ,  H01L21/56 ,  H01L23/3128 ,  H01L21/561 ,  H01L23/3135 ,  H01L25/105 ,  H01L23/293

Abstract: A semiconductor package including an insulating encapsulation, an integrated circuit component, and conductive elements is provided. The integrated circuit component is encapsulated in the insulating encapsulation, wherein the integrated circuit component has at least one through silicon via protruding from the integrated circuit component. The conductive elements are located on the insulating encapsulation, wherein one of the conductive elements is connected to the at least one through silicon via, and the integrated circuit component is electrically connected to the one of the conductive elements through the at least one through silicon via.

公开(公告)号：US20230326917A1

公开(公告)日：2023-10-12

申请号：US18334390

申请日：2023-06-14

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Po-Yao Lin ,  Shu-Shen Yeh ,  Chin-Hua Wang ,  Yu-Sheng Lin ,  Shin-Puu Jeng

IPC: H01L25/18 ,  H01L23/498 ,  H01L25/00 ,  H01L23/31 ,  H01L23/48

CPC classification number: H01L25/18 ,  H01L23/49822 ,  H01L25/50 ,  H01L23/3128 ,  H01L23/481

Abstract: Provided are a package structure and a method of forming the same. The package structure includes a first tier, a second tier, and a third tier. The first tier includes an interposer. The second tier is disposed on the first tier and includes a bottom die. The third tier is disposed on the second tier and includes a plurality of first dies and at least one second die. The at least one second die is disposed between the plurality of first dies. The plurality of first dies are electrically connected to the bottom die by a plurality of first connectors to form a signal path, the plurality of first dies are electrically connected to the interposer by a plurality of second connectors to form a power path, and the plurality of first connectors are closer to the at least one second die than the plurality of second connectors.

公开(公告)号：US11784130B2

公开(公告)日：2023-10-10

申请号：US17459215

申请日：2021-08-27

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yu-Sheng Lin ,  Shin-Puu Jeng ,  Po-Yao Lin ,  Chin-Hua Wang ,  Shu-Shen Yeh ,  Che-Chia Yang

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/683 ,  H01L23/13

CPC classification number: H01L23/5385 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/6835 ,  H01L23/13 ,  H01L23/5383 ,  H01L23/5386 ,  H01L2221/68372

Abstract: A package structure and a formation method of a package structure are provided. The method includes forming a recess in a circuit substrate, and the recess has a first sidewall and a second sidewall. The second sidewall is between the first sidewall and a bottommost surface of the circuit substrate, and the second sidewall is steeper than the first sidewall. The method also includes forming a die package, and the die package has a semiconductor die. The method further includes bonding the die package to the circuit substrate through bonding structures such that a portion of the semiconductor die enters the recess of the circuit substrate. In addition, the method includes forming an underfill material to surround the bonding structures and to fill the recess.

公开(公告)号：US11742298B2

公开(公告)日：2023-08-29

申请号：US16694555

申请日：2019-11-25

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Li-Hsien Huang ,  Hsien-Wei Chen ,  Ching-Wen Hsiao ,  Der-Chyang Yeh ,  Shin-Puu Jeng ,  Chen-Hua Yu

IPC: H01L23/544 ,  H01L23/31 ,  H01L21/48 ,  H01L23/538 ,  H01L23/00 ,  H01L25/10 ,  H01L25/00 ,  H01L23/48 ,  H01L21/768 ,  H01L23/522 ,  H01L21/56 ,  H01L21/78 ,  H01L23/498 ,  H01L21/683 ,  H01L25/065

CPC classification number: H01L23/544 ,  H01L21/486 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/56 ,  H01L21/565 ,  H01L21/6835 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/5226 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/97 ,  H01L25/105 ,  H01L25/50 ,  H01L21/561 ,  H01L23/49816 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0657 ,  H01L2221/68318 ,  H01L2221/68372 ,  H01L2221/68381 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54433 ,  H01L2223/54486 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/83005 ,  H01L2224/83132 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1082 ,  H01L2924/00014 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2224/73265 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2224/97 ,  H01L2224/83 ,  H01L2224/97 ,  H01L2224/73265 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2924/00014 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/15311 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00

Abstract: A package includes a device die, a molding material molding the device die therein, a through-via penetrating through the molding material, and an alignment mark penetrating through the molding material. A redistribution line is on a side of the molding material. The redistribution line is electrically coupled to the through-via.

公开(公告)号：US11728284B2

公开(公告)日：2023-08-15

申请号：US17377583

申请日：2021-07-16

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Po-Chen Lai ,  Chin-Hua Wang ,  Ming-Chih Yew ,  Chia-Kuei Hsu ,  Li-Ling Liao ,  Po-Yao Lin ,  Shin-Puu Jeng

IPC: H01L23/538 ,  H01L23/00 ,  H01L21/48 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L23/562 ,  H01L21/4853 ,  H01L23/5383 ,  H01L23/5386 ,  H01L25/0655 ,  H01L25/50 ,  H01L24/16 ,  H01L24/73 ,  H01L2224/16238 ,  H01L2224/73204

Abstract: A method for forming a chip package structure is provided. The method includes forming a dielectric layer over a redistribution structure. The redistribution structure includes a dielectric structure and a plurality of wiring layers in or over the dielectric structure. The method includes forming a first conductive bump structure and a shield bump structure over the dielectric layer. The first conductive bump structure is electrically connected to the wiring layers, and the shield bump structure is electrically insulated from the wiring layers. The method includes bonding a first chip structure to the redistribution structure through the first conductive bump structure. The first chip structure is electrically insulated from the shield bump structure, and the first chip structure extends across a first sidewall of the shield bump structure.

公开(公告)号：US11721643B2

公开(公告)日：2023-08-08

申请号：US17350317

申请日：2021-06-17

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Po-Chen Lai ,  Chin-Hua Wang ,  Ming-Chih Yew ,  Che-Chia Yang ,  Shu-Shen Yeh ,  Po-Yao Lin ,  Shin-Puu Jeng

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L25/065 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L23/562 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/563 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/16 ,  H01L25/0652 ,  H01L25/0655 ,  H01L2221/68372 ,  H01L2224/16227 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06586 ,  H01L2924/18161 ,  H01L2924/3512

Abstract: A package structure is provided. The package structure includes a redistribution structure and a semiconductor die over the redistribution structure, and bonding elements below the redistribution structure. The semiconductor die has a first sidewall and a second sidewall connected to each other. The bonding elements include a first row of bonding elements and a second row of bonding elements. In a plan view, the second row of bonding elements is arranged between the first row of bonding elements and an extending line of the second sidewall. A minimum distance between the second row of bonding elements and the first sidewall is greater than the minimum distance between the first row of bonding elements and the first sidewall.

公开(公告)号：US11699668B2

公开(公告)日：2023-07-11

申请号：US17318139

申请日：2021-05-12

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shu-Shen Yeh ,  Che-Chia Yang ,  Chia-Kuei Hsu ,  Ming-Chih Yew ,  Po-Yao Lin ,  Shin-Puu Jeng

IPC: H01L23/00 ,  H01L21/48 ,  H01L23/053 ,  H01L23/13

CPC classification number: H01L23/562 ,  H01L21/4878 ,  H01L23/053 ,  H01L23/13

Abstract: A semiconductor device package and a method of forming the same are provided. The semiconductor device package includes a substrate, an electronic component, a ring structure, and an adhesive layer. The electronic component is located over a first surface of the substrate. The ring structure is located over the first surface of the substrate and surrounding the electronic component. The ring structure has a bottom surface facing the first surface of the substrate and a top surface opposite the bottom surface. The ring structure includes a plurality of side parts and a plurality of corner parts recessed from the top surface and thinner than the side parts. Any two of the corner parts are separated from one another by one of the side parts. The adhesive layer is interposed between the bottom surface of the ring structure and the first surface of the substrate.

公开(公告)号：US11676826B2

公开(公告)日：2023-06-13

申请号：US17462505

申请日：2021-08-31

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yu-Sheng Lin ,  Shu-Shen Yeh ,  Chin-Hua Wang ,  Po-Yao Lin ,  Shin-Puu Jeng

IPC: H01L23/58 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00 ,  H01L25/065 ,  H01L23/498

CPC classification number: H01L21/563 ,  H01L21/565 ,  H01L23/3142 ,  H01L23/49838 ,  H01L23/585 ,  H01L24/05 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/04105

Abstract: A semiconductor die package and a method of forming the same are provided. The semiconductor die package includes a package substrate, an interposer substrate over the package substrate, two semiconductor dies over the interposer substrate, and an underfill element formed over the interposer substrate and surrounding the semiconductor dies. A ring structure is disposed over the package substrate and surrounds the semiconductor dies. Recessed parts are recessed from the bottom surface of the ring structure. The recessed parts include multiple first recessed parts arranged in each corner area of the ring structure and two second recessed parts arranged in opposite side areas of the ring structure and aligned with a portion of the underfill element between the semiconductor dies. An adhesive layer is interposed between the bottom surface of the ring structure and the package substrate.

公开(公告)号：US20230178465A1

公开(公告)日：2023-06-08

申请号：US18165928

申请日：2023-02-08

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Kuei Hsu ,  Ming-Chih Yew ,  Shu-Shen Yeh ,  Po-Yao Lin ,  Shin-Puu Jeng

IPC: H01L23/498 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L23/49822 ,  H01L23/3157 ,  H01L21/4857 ,  H01L21/563 ,  H01L24/16 ,  H01L2224/16227

Abstract: A manufacturing method of a semiconductor package includes the following steps. A redistribution structure is formed. An encapsulated semiconductor device is provided on a first side of the redistribution structure, wherein the encapsulated semiconductor device comprising a semiconductor device encapsulated by an encapsulating material. A substrate is bonded to a second side of the redistribution structure opposite to the first side. The redistribution structure includes a plurality of vias connected to one another through a plurality of conductive lines and a redistribution line connected to the plurality of vias, and, from a top view, an angle greater than zero is included between adjacent two of the plurality of conductive lines.