公开(公告)号：US10453832B2

公开(公告)日：2019-10-22

申请号：US15665495

申请日：2017-08-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Ming Wu ,  Kuan-Liang Liu ,  Wen-De Wang ,  Yung-Lung Lin

IPC: H01L25/00 ,  H01L23/58 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L23/31

Abstract: A three-dimensional (3D) integrated circuit (IC) includes a first IC die and a second IC die. The first IC die includes a first semiconductor substrate, and a first interconnect structure over the first semiconductor substrate. The second IC die includes a second semiconductor substrate, and a second interconnect structure that separates the second semiconductor substrate from the first interconnect structure. A seal ring structure separates the first interconnect structure from the second interconnect structure and perimetrically surrounds a gas reservoir between the first IC die and second IC die. The seal ring structure includes a sidewall gas-vent opening structure configured to allow gas to pass between the gas reservoir and an ambient environment surrounding the 3D IC.

公开(公告)号：US20190096848A1

公开(公告)日：2019-03-28

申请号：US15935309

申请日：2018-03-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Xin-Hua Huang ,  Kuan-Liang Liu ,  Kuo Liang Lu ,  Ping-Yin Liu

IPC: H01L23/00 ,  B23K37/04

Abstract: An apparatus and method is provided for controlling a propagation of a bond wave during semiconductor processing. The apparatus has a first chuck to selectively retain a first workpiece. A second chuck selectively retains a second workpiece. The first and second chucks selectively secure at least a periphery of the respective first workpiece and second workpiece. An air vacuum is circumferentially located in a region between the first chuck and second chuck. The air vacuum is configured to induce a vacuum between the first workpiece and second workpiece to selectively bring the first workpiece and second workpiece together from a propagation point. The air vacuum can be localized air vacuum guns, a vacuum disk, or an air curtain positioned about the periphery of the region between the first chuck and second chuck. The air curtain induces a lower pressure within the region between the first and second chucks.

公开(公告)号：US11925033B2

公开(公告)日：2024-03-05

申请号：US17217000

申请日：2021-03-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Liang Liu ,  Sheng-Chau Chen ,  Chung-Liang Cheng ,  Chia-Shiung Tsai ,  Yeong-Jyh Lin ,  Pinyen Lin ,  Huang-Lin Chao

IPC: H01L29/423 ,  H01L21/02 ,  H01L21/285 ,  H01L29/06 ,  H01L29/45 ,  H01L29/66 ,  H01L29/786 ,  H10B61/00

CPC classification number: H10B61/22 ,  H01L21/02603 ,  H01L21/28518 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66742 ,  H01L29/78696

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a first and second transistors arranged over a substrate. The first transistor includes first channel structures extending between first and second source/drain regions. A first gate electrode is arranged between the first channel structures, and a first protection layer is arranged over a topmost one of the first channel structures. The second transistor includes second channel structures extending between the second source/drain region and a third source/drain region. A second gate electrode is arranged between the second channel structures, and a second protection layer is arranged over a topmost one of the second channel structures. The integrated chip further includes a first interconnect structure arranged between the substrate and the first and second channel structures, and a contact plug structure coupled to the second source/drain region and arranged above the first and second gate electrodes.

公开(公告)号：US11710656B2

公开(公告)日：2023-07-25

申请号：US16812533

申请日：2020-03-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ta Wu ,  Kuan-Liang Liu

IPC: H01L21/762 ,  H01L27/12 ,  H01L21/84

CPC classification number: H01L21/76245 ,  H01L21/84 ,  H01L27/1203

Abstract: The present disclosure, in some embodiments, relates to a method of forming a semiconductor structure. The method includes forming a plurality of bulk micro defects within a handle substrate. Sizes of the plurality of bulk micro defects are increased to form a plurality of bulk macro defects (BMDs) within the handle substrate. Some of the plurality of BMDs are removed from within a first denuded region and a second denuded region arranged along opposing surfaces of the handle substrate. An insulating layer is formed onto the handle substrate. A device layer comprising a semiconductor material is formed onto the insulating layer. The first denuded region and the second denuded region vertically surround a central region of the handle substrate that has a higher concentration of the plurality of BMDs than both the first denuded region and the second denuded region.

公开(公告)号：US11532642B2

公开(公告)日：2022-12-20

申请号：US17189709

申请日：2021-03-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Eugene I-Chun Chen ,  Kuan-Liang Liu ,  Szu-Yu Wang ,  Chia-Shiung Tsai ,  Ru-Liang Lee ,  Chih-Ping Chao ,  Alexander Kalnitsky

IPC: H01L27/12 ,  H01L21/762 ,  H01L21/02

Abstract: The present disclosure relates an integrated chip. The integrated chip includes a polysilicon layer arranged on an upper surface of a base substrate. A dielectric layer is arranged over the polysilicon layer, and an active semiconductor layer is arranged over the dielectric layer. A semiconductor material is arranged vertically on the upper surface of the base substrate and laterally beside the active semiconductor layer.

公开(公告)号：US11342322B2

公开(公告)日：2022-05-24

申请号：US16933082

申请日：2020-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Ming Wu ,  Kuan-Liang Liu ,  Wen-De Wang ,  Yung-Lung Lin

IPC: H01L25/00 ,  H01L23/58 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L23/31

Abstract: Some embodiments relate to a three-dimensional (3D) integrated circuit (IC). The 3D IC includes a first IC die comprising a first semiconductor substrate, and a first interconnect structure over the first semiconductor substrate. The 3D IC also includes a second IC die comprising a second semiconductor substrate, and a second interconnect structure that separates the second semiconductor substrate from the first interconnect structure. A seal ring structure separates the first interconnect structure from the second interconnect structure and perimetrically surrounds a gas reservoir between the first IC die and second IC die. The seal ring structure includes a sidewall gas-vent opening structure configured to allow gas to pass between the gas reservoir and an ambient environment surrounding the 3D IC.

公开(公告)号：US10727218B2

公开(公告)日：2020-07-28

申请号：US16201113

申请日：2018-11-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Ming Wu ,  Kuan-Liang Liu ,  Wen-De Wang ,  Yung-Lung Lin

IPC: H01L25/00 ,  H01L23/58 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L23/31

Abstract: Some embodiments relate to a three-dimensional (3D) integrated circuit (IC). The 3D IC includes a first IC die comprising a first semiconductor substrate, and a first interconnect structure over the first semiconductor substrate. The 3D IC also includes a second IC die comprising a second semiconductor substrate, and a second interconnect structure that separates the second semiconductor substrate from the first interconnect structure. A seal ring structure separates the first interconnect structure from the second interconnect structure and perimetrically surrounds a gas reservoir between the first IC die and second IC die. The seal ring structure includes a sidewall gas-vent opening structure configured to allow gas to pass between the gas reservoir and an ambient environment surrounding the 3D IC.

公开(公告)号：US20180175012A1

公开(公告)日：2018-06-21

申请号：US15665495

申请日：2017-08-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Ming Wu ,  Kuan-Liang Liu ,  Wen-De Wang ,  Yung-Lung Lin

IPC: H01L25/00 ,  H01L23/58 ,  H01L23/00

CPC classification number: H01L25/50 ,  H01L23/3114 ,  H01L23/564 ,  H01L23/585 ,  H01L24/29 ,  H01L24/66 ,  H01L24/69 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/89 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/1161 ,  H01L2224/1162 ,  H01L2224/11845 ,  H01L2224/13147 ,  H01L2224/17517 ,  H01L2224/2745 ,  H01L2224/27462 ,  H01L2224/2761 ,  H01L2224/2762 ,  H01L2224/27845 ,  H01L2224/29011 ,  H01L2224/29012 ,  H01L2224/29015 ,  H01L2224/29019 ,  H01L2224/29035 ,  H01L2224/29147 ,  H01L2224/73103 ,  H01L2224/73203 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/81895 ,  H01L2224/83193 ,  H01L2224/83815 ,  H01L2224/83895 ,  H01L2224/8392 ,  H01L2224/83935 ,  H01L2224/83951 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: A three-dimensional (3D) integrated circuit (IC) includes a first IC die and a second IC die. The first IC die includes a first semiconductor substrate, and a first interconnect structure over the first semiconductor substrate. The second IC die includes a second semiconductor substrate, and a second interconnect structure that separates the second semiconductor substrate from the first interconnect structure. A seal ring structure separates the first interconnect structure from the second interconnect structure and perimetrically surrounds a gas reservoir between the first IC die and second IC die. The seal ring structure includes a sidewall gas-vent opening structure configured to allow gas to pass between the gas reservoir and an ambient environment surrounding the 3D IC.

公开(公告)号：US11676969B2

公开(公告)日：2023-06-13

申请号：US17192333

申请日：2021-03-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Liang Liu ,  Yeur-Luen Tu

IPC: H01L27/12 ,  H01L21/762

CPC classification number: H01L27/1203 ,  H01L21/76256

Abstract: Various embodiments of the present disclosure are directed towards a semiconductor wafer. The semiconductor wafer comprises a handle wafer. A first oxide layer is disposed over the handle wafer. A device layer is disposed over the first oxide layer. A second oxide layer is disposed between the first oxide layer and the device layer, wherein the first oxide layer has a first etch rate for an etch process and the second oxide layer has a second etch rate for the etch process, and wherein the second etch rate is greater than the first etch rate.

公开(公告)号：US20220189997A1

公开(公告)日：2022-06-16

申请号：US17189709

申请日：2021-03-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Eugene I-Chun Chen ,  Kuan-Liang Liu ,  Szu-Yu Wang ,  Chia-Shiung Tsai ,  Ru-Liang Lee ,  Chih-Ping Chao ,  Alexander Kalnitsky

IPC: H01L27/12 ,  H01L21/762

Abstract: The present disclosure relates an integrated chip. The integrated chip includes a polysilicon layer arranged on an upper surface of a base substrate. A dielectric layer is arranged over the polysilicon layer, and an active semiconductor layer is arranged over the dielectric layer. A semiconductor material is arranged vertically on the upper surface of the base substrate and laterally beside the active semiconductor layer.