公开(公告)号：US20240153901A1

公开(公告)日：2024-05-09

申请号：US18151714

申请日：2023-01-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hung Lin ,  Han-Jong Chia ,  Wei-Ming Wang ,  Kuo-Chung Yee ,  Chen Chen ,  Shih-Peng Tai

IPC: H01L23/00

CPC classification number: H01L24/08 ,  H01L24/05 ,  H01L24/80 ,  H01L24/13 ,  H01L2224/05553 ,  H01L2224/05555 ,  H01L2224/05556 ,  H01L2224/05571 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05649 ,  H01L2224/05657 ,  H01L2224/05666 ,  H01L2224/0568 ,  H01L2224/05684 ,  H01L2224/0603 ,  H01L2224/06181 ,  H01L2224/06505 ,  H01L2224/08123 ,  H01L2224/08147 ,  H01L2224/13147 ,  H01L2224/80357 ,  H01L2224/80379 ,  H01L2224/80896 ,  H01L2924/04642 ,  H01L2924/0544 ,  H01L2924/059

Abstract: A first and second semiconductor device are bonded together using a bonding contact pad embedded within a bonding dielectric layer of the first semiconductor device and at least one bonding via embedded within a bonding dielectric layer of the second semiconductor device. The bonding contact pad extends a first dimension in a first direction perpendicular to the major surface of the first semiconductor device and a second dimension in a second direction parallel to the plane of the first semiconductor wafer, the second dimension being at least twice the first dimension. The bonding via extends a third dimension in the first direction and a fourth dimension in the second direction, the third dimension being at least twice the first dimension. The bonding contact pad and bonding via may be at least partially embedded in respective bonding dielectric layers in respective topmost dielectric layers of respective stacked interconnect layers.

公开(公告)号：US20240087953A1

公开(公告)日：2024-03-14

申请号：US18518081

申请日：2023-11-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hung Lin ,  Sheng-Hsuan Lin ,  Chih-Wei Chang ,  You-Hua Chou

IPC: H01L21/768 ,  H01L21/285 ,  H01L23/485 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76858 ,  H01L21/28518 ,  H01L21/76846 ,  H01L21/76852 ,  H01L21/76855 ,  H01L21/76871 ,  H01L21/76883 ,  H01L21/76889 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/53238 ,  H01L2221/1073 ,  H01L2924/0002

Abstract: A semiconductor device and method of formation are provided. The semiconductor device comprises a silicide layer over a substrate, a metal plug in an opening defined by a dielectric layer over the substrate, a first metal layer between the metal plug and the dielectric layer and between the metal plug and the silicide layer, a second metal layer over the first metal layer, and an amorphous layer between the first metal layer and the second metal layer.

公开(公告)号：US20240047216A1

公开(公告)日：2024-02-08

申请号：US17816782

申请日：2022-08-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Ming Wang ,  Yu-Hung Lin ,  Shih-Peng Tai ,  Kuo-Chung Yee

IPC: H01L21/308 ,  H01L21/311 ,  H01L23/00

CPC classification number: H01L21/308 ,  H01L21/31144 ,  H01L24/80 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: A method includes forming an etching mask over a first wafer. The etching mask covers an inner portion of the first wafer. A wafer edge trimming process is performed to trim an edge portion of the first wafer, with the etching mask protecting the inner portion of the first wafer from being etched. The edge portion forms a full ring encircling the inner portion of the first wafer. The method further includes removing the etching mask, and bonding the first wafer to a second wafer.

公开(公告)号：US20240014091A1

公开(公告)日：2024-01-11

申请号：US17861556

申请日：2022-07-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Wei-Ming Wang ,  Yu-Hung Lin ,  Shih-Peng Tai ,  Kuo-Chung Yee

IPC: H01L23/367 ,  H01L23/00 ,  H01L23/48 ,  H01L25/065

CPC classification number: H01L23/367 ,  H01L24/08 ,  H01L23/481 ,  H01L25/0657 ,  H01L24/05 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/08145 ,  H01L2224/08245 ,  H01L2224/06181 ,  H01L2224/0557 ,  H01L2224/80896 ,  H01L24/80 ,  H01L24/32 ,  H01L2224/32245 ,  H01L2224/2929 ,  H01L2224/29393 ,  H01L2224/29193 ,  H01L24/29 ,  H01L23/3675 ,  H01L2225/06589

Abstract: A semiconductor device includes an integrated circuit structure and a thermal pillar over the integrated circuit structure. The integrated circuit structure includes a semiconductor substrate including circuitry, a dielectric layer over the semiconductor substrate, an interconnect structure over the dielectric layer, and a first thermal fin extending through the semiconductor substrate, the dielectric layer, and the interconnect structure. The first thermal fin is electrically isolated from the circuitry. The thermal pillar is thermally coupled to the first thermal fin.

公开(公告)号：US11682625B2

公开(公告)日：2023-06-20

申请号：US17359083

申请日：2021-06-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hung Lin ,  Chi-Wen Liu ,  Horng-Huei Tseng

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/535 ,  H01L21/768 ,  H01L23/532 ,  H01L21/285 ,  H01L29/66 ,  H01L29/417 ,  H01L27/092 ,  H01L29/786 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/45 ,  H01L23/485

CPC classification number: H01L23/535 ,  H01L21/28518 ,  H01L21/76805 ,  H01L21/76889 ,  H01L21/76895 ,  H01L21/823821 ,  H01L23/53266 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/41733 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/78696 ,  H01L21/76843 ,  H01L21/76855 ,  H01L23/485 ,  H01L29/458 ,  H01L29/66545

Abstract: A semiconductor device includes a semiconductor substrate comprising a contact region, a silicide present on the contact region, a dielectric layer present on the semiconductor substrate, the dielectric layer comprising an opening to expose a portion of the contact region, a conductor present in the opening, a barrier layer present between the conductor and the dielectric layer, and a metal layer present between the barrier layer and the dielectric layer, wherein a Si concentration of the silicide is varied along a height of the silicide.

公开(公告)号：US20190279939A1

公开(公告)日：2019-09-12

申请号：US16416454

申请日：2019-05-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hung Lin ,  Chi-Wen Liu ,  Horng-Huei Tseng

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/535 ,  H01L27/12 ,  H01L27/092 ,  H01L29/78 ,  H01L21/84 ,  H01L21/8238 ,  H01L29/417 ,  H01L23/485 ,  H01L21/285 ,  H01L21/3065 ,  H01L23/528

Abstract: A semiconductor device includes a semiconductor substrate, a contact region present in the semiconductor substrate, and a silicide present on a textured surface of the contact region. A plurality of sputter ions is present between the silicide and the contact region. Since the surface of the contact region is textured, the contact area provided by the silicide is increased accordingly, thus the resistance of a interconnection structure in the semiconductor device is reduced.

公开(公告)号：US10297548B2

公开(公告)日：2019-05-21

申请号：US15382492

申请日：2016-12-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Hung Lin ,  Chi-Wen Liu ,  Horng-Huei Tseng

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/532 ,  H01L23/535 ,  H01L21/768 ,  H01L21/3065 ,  H01L23/528 ,  H01L21/285 ,  H01L23/485 ,  H01L29/417

Abstract: A semiconductor device includes a semiconductor substrate, an epitaxy structure present in the semiconductor substrate, and a silicide present on a textured surface of the epitaxy structure. A plurality of sputter ions are present between the silicide and the epitaxy structure. Since the surface of the epitaxy structure is textured, the contact area provided by the silicide is increased accordingly, thus the resistance of a interconnection structure in the semiconductor device is reduced.

公开(公告)号：US09773779B2

公开(公告)日：2017-09-26

申请号：US14856813

申请日：2015-09-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： I-Tseng Chen ,  Hon-Lin Huang ,  Chun-Hsien Huang ,  Yu-Hung Lin

IPC: H01L21/20 ,  H01L27/06 ,  H01L21/8234 ,  H01L21/02 ,  H01L49/02

CPC classification number: H01L27/0629 ,  H01L21/02271 ,  H01L21/823437 ,  H01L28/20

Abstract: A semiconductor device structure including a resistor layer is provided. The semiconductor device structure includes a gate structure formed over the first region of the substrate and an inter-layer dielectric (ILD) layer formed adjacent to the gate structure. The semiconductor device structure further includes a resistor layer is formed over the ILD layer over the second region of the substrate, and the major structure of the resistor layer is amorphous.

公开(公告)号：US20250031434A1

公开(公告)日：2025-01-23

申请号：US18353389

申请日：2023-07-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hung Lin ,  Jih-Churng Twu ,  Su-Chun Yang ,  Shih-Peng Tai ,  Yu-Hao Kuo

IPC: H01L21/822 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065

Abstract: A method includes bonding a first semiconductor die and a second semiconductor die to a substrate, where a gap is disposed between a first sidewall of the first semiconductor die and a second sidewall of the second semiconductor die, performing a plasma treatment to dope top surfaces and sidewalls of each of the first semiconductor die and the second semiconductor die with a first dopant, where a concentration of the first dopant in the first sidewall decreases in a vertical direction from a top surface of the first semiconductor die towards a bottom surface of the first semiconductor die, and a concentration of the first dopant in the second sidewall decreases in a vertical direction from a top surface of the second semiconductor die towards a bottom surface of the second semiconductor die, and filling the gap with a spin-on dielectric material.

公开(公告)号：US20240096830A1

公开(公告)日：2024-03-21

申请号：US18151663

申请日：2023-01-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Yi Huang ,  Yu-Hung Lin ,  Wei-Ming Wang ,  Chen Chen ,  Shih-Peng Tai ,  Kuo-Chung Yee

IPC: H01L23/00 ,  H01L21/304 ,  H01L25/065

CPC classification number: H01L24/08 ,  H01L21/3043 ,  H01L24/03 ,  H01L24/80 ,  H01L24/94 ,  H01L25/0657 ,  H01L2224/0221 ,  H01L2224/03019 ,  H01L2224/03831 ,  H01L2224/0384 ,  H01L2224/03845 ,  H01L2224/08145 ,  H01L2224/80007 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/94 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/3512

Abstract: A method includes forming a first sealing layer at a first edge region of a first wafer; and bonding the first wafer to a second wafer to form a wafer stack. At a time after the bonding, the first sealing layer is between the first edge region of the first wafer and a second edge region of the second wafer, with the first edge region and the second edge region comprising bevels. An edge trimming process is then performed on the wafer stack. After the edge trimming process, the second edge region of the second wafer is at least partially removed, and a portion of the first sealing layer is left as a part of the wafer stack. An interconnect structure is formed as a part of the second wafer. The interconnect structure includes redistribution lines electrically connected to integrated circuit devices in the second wafer.