公开(公告)号：US10668592B2

公开(公告)日：2020-06-02

申请号：US15003258

申请日：2016-01-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Bo-I Lee ,  Soon-Kang Huang ,  Chi-Ming Yang ,  Chin-Hsiang Lin

IPC: B24B37/20 ,  B24B53/017

Abstract: A method of planarizing a wafer includes pressing the wafer against a planarization pad. The method further includes moving the planarization pad relative to the wafer. The method further includes conditioning the planarization pad using a pad conditioner. Conditioning the planarization pad includes moving the planarization pad relative to the pad conditioner. The pad conditioner includes abrasive particles having aligned tips a substantially constant distance from a surface of substrate of the pad conditioner.

公开(公告)号：US10514247B2

公开(公告)日：2019-12-24

申请号：US15864458

申请日：2018-01-08

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Wei-Hsiang Tseng ,  Chin-Hsiang Lin ,  Heng-Hsin Liu ,  Jui-Chun Peng ,  Ho-Ping Chen

IPC: G01B11/02 ,  G03F9/00 ,  H01L23/544

Abstract: A wafer alignment apparatus includes a light source, a light detection device, and a rotation device configured to rotate a wafer. The light source is configured to provide a light directed to the wafer. The light detection device is configured to detect reflected light intensity from the wafer to locate at least one wafer alignment mark of wafer alignment marks separated by a plurality of angles. At least two of those angles are equal.

公开(公告)号：US10164114B2

公开(公告)日：2018-12-25

申请号：US15991680

申请日：2018-05-29

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chin-Hsiang Lin ,  Tai-Chun Huang ,  Tien-I Bao

IPC: H01L29/78 ,  H01L29/66 ,  H01L23/528 ,  H01L21/8234 ,  H01L21/02 ,  H01L21/768 ,  H01L21/033

Abstract: An embodiment is a method including recessing a gate electrode over a semiconductor fin on a substrate to form a first recess from a top surface of a dielectric layer, forming a first mask in the first recess over the recessed gate electrode, recessing a first conductive contact over a source/drain region of the semiconductor fin to form a second recess from the top surface of the dielectric layer, and forming a second mask in the second recess over the recessed first conductive contact.

公开(公告)号：US09865429B2

公开(公告)日：2018-01-09

申请号：US14541314

申请日：2014-11-14

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Hong Hwang ,  Chun-Lin Chang ,  Nai-Han Cheng ,  Chi-Ming Yang ,  Chin-Hsiang Lin

IPC: H01J3/02 ,  H01J37/317 ,  H01J3/26 ,  H01J37/02 ,  H01J37/06

CPC classification number: H01J37/3171 ,  H01J3/02 ,  H01J3/022 ,  H01J3/26 ,  H01J37/026 ,  H01J37/06 ,  H01J2237/0041 ,  H01J2237/31705

Abstract: The present disclosure provides for various advantageous methods and apparatus of controlling electron emission. One of the broader forms of the present disclosure involves an electron emission element, comprising an electron emitter including an electron emission region disposed between a gate electrode and a cathode electrode. An anode is disposed above the electron emission region, and a voltage set is disposed above the anode. A first voltage applied between the gate electrode and the cathode electrode controls a quantity of electrons generated from the electron emission region. A second voltage applied to the anode extracts generated electrons. A third voltage applied to the voltage set controls a direction of electrons extracted through the anode.

公开(公告)号：US09863754B2

公开(公告)日：2018-01-09

申请号：US14486514

申请日：2014-09-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Wei-Hsiang Tseng ,  Chin-Hsiang Lin ,  Heng-Hsin Liu ,  Jui-Chun Peng ,  Ho-Ping Cheng

IPC: G01B11/00 ,  G01B11/02 ,  G03F9/00 ,  H01L23/544

CPC classification number: G01B11/02 ,  G03F9/7011 ,  G03F9/7084 ,  H01L23/544 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A wafer alignment apparatus includes a light source, a light detection device, and a rotation device configured to rotate a wafer. The light source is configured to provide light directed to the wafer. The light detection device is configured to detect reflected light intensity from the wafer to locate at least one wafer alignment mark of wafer alignment marks separated by a plurality of angles. At least two of those angles are equal.

公开(公告)号：US09818603B2

公开(公告)日：2017-11-14

申请号：US14199595

申请日：2014-03-06

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Wei-Chi Lin ,  Chin-Hsiang Lin ,  Neng-Kuo Chen ,  Sey-Ping Sun

IPC: H01L21/02 ,  H01L27/088 ,  H01L21/28 ,  H01L29/51 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/12 ,  H01L29/165

CPC classification number: H01L21/0234 ,  H01L21/02164 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/02337 ,  H01L21/02348 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28255 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823462 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/165 ,  H01L29/513 ,  H01L29/517

Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a method of manufacturing a semiconductor device includes providing a substrate, the substrate includes a first fin, a second fin, and an isolation region disposed between the first fin and the second fin. The second fin includes a different material than a material of the substrate. The method includes forming an oxide over the first fin, the second fin, and a top surface of the isolation region at a temperature of about 400 degrees C. or less, and post-treating the oxide at a temperature of about 600 degrees C. or less.

公开(公告)号：US09810990B2

公开(公告)日：2017-11-07

申请号：US14658354

申请日：2015-03-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Wei-Han Lai ,  Ching-Yu Chang ,  Cheng-Han Wu ,  Siao-Shan Wang ,  Chin-Hsiang Lin

IPC: G03F7/38 ,  G03F7/32 ,  G03F7/40 ,  G03F7/038

CPC classification number: G03F7/325 ,  G03F7/0382 ,  G03F7/38 ,  G03F7/40

Abstract: A material layer is formed over a substrate. A negative tone photoresist layer is formed over the material layer. An exposure process is performed to the negative tone photoresist layer. A post-exposure bake (PEB) process is performed to the negative tone photoresist layer. After the exposure process and the PEB process, the negative tone photoresist layer is treated with a solvent. The solvent contains a chemical having a greater dipole moment than n-butyl acetate (n-BA).

公开(公告)号：US09601587B2

公开(公告)日：2017-03-21

申请号：US14603861

申请日：2015-01-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Sey-Ping Sun ,  Tsung-Lin Lee ,  Chin-Hsiang Lin ,  Chih-Hao Chang ,  Chen-Nan Yeh ,  Chao-An Jong

IPC: H01L29/423 ,  H01L21/768 ,  H01L29/49 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/4232 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76897 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/78

Abstract: A semiconductor device includes a gate stack overlying a substrate. The semiconductor device further includes a spacer on sidewalls of the gate stack, where a top surface of the spacer is above a top surface of the gate stack. Additionally, the semiconductor device includes a protection layer overlying the gate stack and filling at least a portion of a space surrounded by the spacer above the top surface of the gate stack. Furthermore, the semiconductor device includes a contact hole over the spacer, where the contact hole extends over the gate stack, and where a sidewall of the contact hole has a step-wise shape.

公开(公告)号：US20160099331A1

公开(公告)日：2016-04-07

申请号：US14968652

申请日：2015-12-14

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Clement Hsingjen Wann ,  Sey-Ping Sun ,  Ling-Yen Yeh ,  Chi-Yuan Shih ,  Li-Chi Yu ,  Chun Hsiung Tsai ,  Chin-Hsiang Lin ,  Neng-Kuo Chen ,  Meng-Chun Chang ,  Ta-Chun Ma ,  Gin-Chen Huang ,  Yen-Chun Huang

IPC: H01L29/45 ,  H01L29/161 ,  H01L29/417 ,  H01L27/088

CPC classification number: H01L21/28518 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/161 ,  H01L29/41791 ,  H01L29/45 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A device having an epitaxial region and dual metal-semiconductor alloy surfaces is provided. The epitaxial region includes an upward facing facet and a downward facing facet. The upward facing facet has a first metal-semiconductor alloy surface and the downward facing facet has a second metal-semiconductor alloy surface, wherein the first metal-semiconductor alloy is different than the second metal-semiconductor alloy.

Abstract translation: 提供具有外延区域和双金属 - 半导体合金表面的器件。 外延区域包括面向上的小面和面向下的小面。 面向上的小面具有第一金属 - 半导体合金表面，并且朝下小面具有第二金属 - 半导体合金表面，其中第一金属 - 半导体合金不同于第二金属 - 半导体合金。

公开(公告)号：US09214543B2

公开(公告)日：2015-12-15

申请号：US13915184

申请日：2013-06-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Simon Su-Horng Lin ,  Chi-Ming Yang ,  Chyi Shyuan Chern ,  Chin-Hsiang Lin

IPC: H01L29/78 ,  H01L29/49 ,  C23C14/02 ,  C23C14/04 ,  C23C14/18 ,  C23C14/22 ,  C23C16/02 ,  C23C16/04 ,  C23C16/06 ,  C23C16/48 ,  H01L21/28 ,  H01L21/285 ,  H01L21/768 ,  H01L29/66

CPC classification number: H01L29/78 ,  C23C14/022 ,  C23C14/046 ,  C23C14/18 ,  C23C14/221 ,  C23C16/0263 ,  C23C16/045 ,  C23C16/06 ,  C23C16/48 ,  C23C16/484 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/76843 ,  H01L21/76856 ,  H01L21/76862 ,  H01L21/76865 ,  H01L21/76877 ,  H01L29/4966 ,  H01L29/66545

Abstract: A gate structure including a substrate and a gate dielectric layer formed over the substrate. The gate structure further includes a workfunction layer over the gate dielectric layer and spacers enclosing the gate dielectric layer and the workfunction layer. A top surface of a portion of the workfunction layer in contact with sidewalls of the spacer is a same distance from the gate dielectric layer as a top surface of a center portion of the work function layer.

Abstract translation: 一种栅极结构，包括在基板上形成的基板和栅极电介质层。 栅极结构还包括在栅极电介质层上的功函数层和包围栅极介电层和功函数层的间隔物。 与间隔物的侧壁接触的功函数层的一部分的顶表面与作为功函数层的中心部分的顶表面的栅介电层相同。