公开(公告)号：US09520304B2

公开(公告)日：2016-12-13

申请号：US14074148

申请日：2013-11-07

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Hong-Da Chang ,  Yi-Che Lai ,  Chi-Hsin Chiu ,  Shih-Kuang Chiu

IPC: H01L23/28 ,  H01L21/48 ,  H01L23/00 ,  H01L23/538 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L21/4857 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/5383 ,  H01L24/97 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2924/351 ,  H01L2224/83 ,  H01L2224/81 ,  H01L2924/00

Abstract: A fabrication method of a semiconductor package is disclosed, which includes the steps of: providing a semiconductor structure having a carrier, a circuit portion formed on the carrier and a plurality of semiconductor elements disposed on the circuit portion; disposing a lamination member on the semiconductor elements; forming an insulating layer on the circuit portion for encapsulating the semiconductor elements; and removing the carrier. The lamination member increases the strength between adjacent semiconductor elements so as to overcome the conventional cracking problem caused by a CTE mismatch between the semiconductor elements and the insulating layer when the carrier is removed.

Abstract translation: 公开了一种半导体封装的制造方法，其包括以下步骤：提供具有载体的半导体结构，形成在载体上的电路部分和设置在电路部分上的多个半导体元件; 在所述半导体元件上设置层压部件; 在用于封装半导体元件的电路部分上形成绝缘层; 并移除载体。 层叠构件增加相邻半导体元件之间的强度，以克服当移除载体时由半导体元件和绝缘层之间的CTE失配引起的常规裂纹问题。

公开(公告)号：US09502333B2

公开(公告)日：2016-11-22

申请号：US14056230

申请日：2013-10-17

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Meng-Tsung Lee ,  Yi-Che Lai ,  Shih-Kuang Chiu

IPC: H01L23/48 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L24/14 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/498 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L2224/13 ,  H01L2224/1401 ,  H01L2224/1412 ,  H01L2924/15788 ,  H01L2924/00

Abstract: A semiconductor device is provided, including: a substrate having opposing first and second surfaces and a plurality of conductive vias passing through the first and second surfaces; an insulating layer formed on the first surface of the substrate and exposing end portions of the conductive vias therefrom; and a buffer layer formed on the insulating layer at peripheries of the end portions of the conductive vias, thereby increasing product reliability and good yield.

Abstract translation: 提供一种半导体器件，包括：具有相对的第一和第二表面的衬底和穿过第一和第二表面的多个导电通孔; 绝缘层，形成在所述基板的所述第一表面上，并暴露所述导电通孔的端部; 以及在导电通孔的端部的周边形成在绝缘层上的缓冲层，从而提高产品的可靠性和良好的产率。

公开(公告)号：US09349705B2

公开(公告)日：2016-05-24

申请号：US14616078

申请日：2015-02-06

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chien-Feng Chan ,  Mu-Hsuan Chan ,  Chun-Tang Lin ,  Yi-Che Lai

IPC: H01L21/4763 ,  H01L23/00 ,  H01L23/488 ,  H01L21/441 ,  H01L21/56 ,  H01L23/14

CPC classification number: H01L24/81 ,  H01L21/441 ,  H01L21/56 ,  H01L23/145 ,  H01L23/147 ,  H01L23/488 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/05572 ,  H01L2224/13022 ,  H01L2224/13084 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81805 ,  H01L2224/81815 ,  H01L2224/81986 ,  H01L2224/83104 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/9211 ,  H01L2224/92125 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/01047 ,  H01L2924/01029

Abstract: A conductive bump structure used to be formed on a substrate having a plurality of bonding pads. The conductive bump structure includes a first metal layer formed on the bonding pads, a second metal layer formed on the first metal layer, and a third metal layer formed on the second metal layer. The second metal layer has a second melting point higher than a third melting point of the third metal layer. Therefore, a thermal compression bonding process is allowed to be performed to the third metal layer first so as to bond the substrate to another substrate, and then a reflow process can be performed to melt the second metal layer and the third metal layer into each other so as to form an alloy portion, thus avoiding cracking of the substrate.

Abstract translation: 用于形成在具有多个接合焊盘的基板上的导电凸块结构。 导电凸块结构包括在接合焊盘上形成的第一金属层，形成在第一金属层上的第二金属层和形成在第二金属层上的第三金属层。 第二金属层的第二熔点高于第三金属层的第三熔点。 因此，首先对第三金属层进行热压接，从而将基板粘合到另一基板上，然后进行回流处理，使第二金属层和第三金属层彼此熔融 从而形成合金部分，从而避免基板的开裂。

公开(公告)号：US09269693B2

公开(公告)日：2016-02-23

申请号：US14604128

申请日：2015-01-23

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chien-Feng Chan ,  Chun-Tang Lin ,  Yi-Che Lai

IPC: H01L33/06 ,  H01L23/00 ,  H01L23/498 ,  H01L49/02 ,  H01L21/56 ,  H01L25/065 ,  H01L25/00 ,  H01L21/78 ,  H01L23/31

CPC classification number: H01L24/94 ,  H01L21/561 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/49816 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L28/00 ,  H01L2224/0231 ,  H01L2224/12105 ,  H01L2224/13025 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16265 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92225 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2924/05432 ,  H01L2924/05442 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/141 ,  H01L2924/1421 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/18161 ,  H01L2924/19103 ,  H01L2924/3511 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor package is provided. The semiconductor package includes a semiconductor chip having opposite first and second surfaces; an RDL structure formed on the first surface of the semiconductor chip and having opposite third and fourth surfaces and a plurality of first conductive through holes penetrating the third and fourth surfaces thereof, wherein the RDL structure is formed on the semiconductor chip through the fourth surface thereof and electrically connected to the semiconductor chip through a plurality of first conductive elements, and the third surface of the RDL structure has a redistribution layer formed thereon; a plurality of conductive bumps formed on the redistribution layer; and an encapsulant formed on the first surface of the semiconductor chip for encapsulating the RDL structure, wherein the conductive bumps are embedded in and exposed from the encapsulant. The invention effectively prevents warpage of the semiconductor package and improves the electrical connection significantly.

Abstract translation: 提供半导体封装。 半导体封装包括具有相反的第一和第二表面的半导体芯片; 形成在半导体芯片的第一表面上并且具有相反的第三和第四表面的RDL结构以及穿过其第三和第四表面的多个第一导电通孔，其中RDL结构通过其第四表面形成在半导体芯片上 并通过多个第一导电元件与半导体芯片电连接，并且RDL结构的第三表面在其上形成再分布层; 形成在再分配层上的多个导电凸块; 以及密封剂，其形成在所述半导体芯片的用于封装所述RDL结构的所述第一表面上，其中所述导电凸块嵌入并暴露于所述密封剂。 本发明有效地防止了半导体封装的翘曲，并显着地改善了电连接。

公开(公告)号：US08987012B2

公开(公告)日：2015-03-24

申请号：US13845698

申请日：2013-03-18

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Pin-Cheng Huang ,  Chun-Tang Lin ,  Wen-Tsung Tseng ,  Yi-Che Lai

IPC: H01L21/66

CPC classification number: H01L22/14 ,  H01L21/6836 ,  H01L22/20 ,  H01L23/147 ,  H01L23/367 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/97 ,  H01L25/0655 ,  H01L2221/68331 ,  H01L2221/68381 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81005 ,  H01L2224/8181 ,  H01L2224/81815 ,  H01L2224/83005 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/16195 ,  H01L2924/351 ,  H01L2924/37001 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L2224/81

Abstract: A method of testing a semiconductor package is provided, including: disposing at least an interposer on a top surface of an adhesive layer, the interposer having a first surface and a second surface opposite to the first surface, a plurality of conductive elements disposed between the second surface of the interposer and the adhesive layer; disposing at least a semiconductor chip on the first surface of the interposer, and performing an electrical test on the semiconductor chip via the conductive elements, wherein if there are a plurality of semiconductor chips that are disposed on the first surface of the interposer, the step of disposing the semiconductor chip and performing the electrical test on the semiconductor chip is iterated; and removing the adhesive layer. By using the method, the fabrication cost and equipment cost of the semiconductor package are reduced, and product yield is increased.

Abstract translation: 提供了一种测试半导体封装的方法，包括：至少在粘合剂层的顶表面上设置插入件，所述插入件具有第一表面和与第一表面相对的第二表面，多个导电元件设置在第二表面之间 插入器的第二表面和粘合剂层; 在所述插入件的第一表面上设置至少一个半导体芯片，并且经由所述导电元件对所述半导体芯片进行电测试，其中如果存在设置在所述插入件的第一表面上的多个半导体芯片，则所述步骤 重复设置半导体芯片并对半导体芯片进行电气测试; 并去除粘合剂层。 通过使用该方法，半导体封装的制造成本和设备成本降低，产品产量增加。

公开(公告)号：US20150069628A1

公开(公告)日：2015-03-12

申请号：US14259629

申请日：2014-04-23

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Wen-Tsung Tseng ,  Yi-Che Lai ,  Shih-Kuang Chiu ,  Mao-Hua Yeh

IPC: H01L23/498 ,  H01L21/768

CPC classification number: H01L23/49827 ,  H01L21/481 ,  H01L21/4853 ,  H01L23/13 ,  H01L23/147 ,  H01L23/15 ,  H01L23/3738 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49894 ,  H01L2224/11

Abstract: A semiconductor package is provided, including a semiconductor substrate having a plurality of conductive vias, a buffer layer formed on the semiconductor substrate, a plurality of conductive pads formed on end surfaces of the conductive vias and covering the buffer layer. During a reflow process, the buffer layer greatly reduces the thermal stress, thereby eliminating the occurance of cracking at the interface of conductive pads. A method of fabricating such a semiconductor package is also provided.

Abstract translation: 提供一种半导体封装，包括具有多个导电通孔的半导体衬底，形成在半导体衬底上的缓冲层，形成在导电通孔的端表面上并覆盖缓冲层的多个导电焊盘。 在回流过程中，缓冲层大大降低了热应力，从而消除了导电焊盘界面处的开裂现象。 还提供了一种制造这种半导体封装的方法。

公开(公告)号：US20140027926A1

公开(公告)日：2014-01-30

申请号：US13872468

申请日：2013-04-29

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Wang-Ting Chen ,  Mu-Hsuan Chan ,  Yi-Chian Liao ,  Chun-Tang Lin ,  Yi-Che Lai

IPC: H01L23/28 ,  H01L23/538 ,  H01L21/56

CPC classification number: H01L21/561 ,  H01L21/56 ,  H01L21/563 ,  H01L21/565 ,  H01L21/78 ,  H01L23/28 ,  H01L23/31 ,  H01L23/3121 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/5384 ,  H01L24/81 ,  H01L24/83 ,  H01L24/94 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/06181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/10253 ,  H01L2924/157 ,  H01L2924/15788 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2224/81

Abstract: A semiconductor package is provided, including: a carrier; at least an interposer disposed on the carrier; an encapsulant formed on the carrier for encapsulating the interposer while exposing a top side of the interposer; a semiconductor element disposed on the top side of the interposer; and an adhesive formed between the interposer and the semiconductor element. By encapsulating the interposer with the encapsulant, warpage of the interposer is avoided and a planar surface is provided for the semiconductor element to be disposed thereon, thereby improving the reliability of electrical connection between the interposer and the semiconductor element.

Abstract translation: 提供半导体封装，包括：载体; 至少设置在所述载体上的插入件; 形成在所述载体上的密封剂，用于在暴露所述插入件的顶侧的同时封装所述插入件; 设置在所述插入件的顶侧的半导体元件; 以及形成在插入件和半导体元件之间的粘合剂。 通过用封装剂封装插入件，避免了插入器的翘曲，并且为了将半导体元件设置在其上提供平坦的表面，从而提高了插入件与半导体元件之间的电连接的可靠性。

公开(公告)号：US09754898B2

公开(公告)日：2017-09-05

申请号：US13922828

申请日：2013-06-20

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Mu-Hsuan Chan ,  Wan-Ting Chen ,  Chun-Tang Lin ,  Yi-Che Lai

IPC: H01L21/00 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L23/562 ,  H01L21/563 ,  H01L21/565 ,  H01L23/3114 ,  H01L24/97 ,  H01L2224/16225 ,  H01L2924/351 ,  H01L2924/00

Abstract: A semiconductor package is provided, which includes: a carrier; at least an interposer disposed on the carrier; an encapsulant formed on the carrier for encapsulating the interposer while exposing a top surface of the interposer; a redistribution layer formed on the encapsulant and the top surface of the interposer; and at least a semiconductor element disposed on the redistribution layer. The top surface of the interposer is flush with a surface of the encapsulant so as for the redistribution layer to have a planar surface for disposing the semiconductor element, thereby preventing warpage of the interposer and improving the reliability of electrical connection between the redistribution layer and the semiconductor element.

公开(公告)号：US09627226B2

公开(公告)日：2017-04-18

申请号：US15078418

申请日：2016-03-23

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chun-Tang Lin ,  Yi-Che Lai

IPC: H01L25/00 ,  H01L21/52 ,  H01L21/56 ,  H01L21/78 ,  H01L25/065 ,  H01L21/48 ,  H01L23/498 ,  H01L23/48 ,  H01L23/31

CPC classification number: H01L25/50 ,  H01L21/486 ,  H01L21/52 ,  H01L21/563 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/49833 ,  H01L25/065 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/00

Abstract: A fabrication method of a semiconductor package is disclosed, which includes the steps of: disposing a plurality of first semiconductor elements on an interposer; forming a first encapsulant on the interposer for encapsulating the first semiconductor elements; disposing a plurality of second semiconductor elements on the first semiconductor elements; forming a second encapsulant on the first semiconductor elements and the first encapsulant for encapsulating the second semiconductor elements; and thinning the interposer, thereby reducing the overall stack thickness and preventing warpage of the interposer.

公开(公告)号：US20160118271A1

公开(公告)日：2016-04-28

申请号：US14986903

申请日：2016-01-04

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Kuan-Wei Chuang ,  Chun-Tang Lin ,  Yi-Chian Liao ,  Yi-Che Lai

IPC: H01L21/48 ,  H01L21/683 ,  H01L21/78 ,  H01L23/498 ,  H01L23/00 ,  H01L21/311 ,  H01L21/56 ,  H01L25/00

CPC classification number: H01L21/486 ,  H01L21/31111 ,  H01L21/4853 ,  H01L21/563 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/147 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49872 ,  H01L24/03 ,  H01L24/08 ,  H01L24/11 ,  H01L24/17 ,  H01L24/97 ,  H01L25/50 ,  H01L2224/02317 ,  H01L2224/02372 ,  H01L2224/03002 ,  H01L2224/08235 ,  H01L2224/16 ,  H01L2224/16245 ,  H01L2924/351 ,  H01L2924/00

Abstract: A method of fabricating a semiconductor package is provided, including: cutting a substrate into a plurality of interposers; disposing the interposers in a plurality of openings of a carrier, wherein the openings are spaced from one another by a distance; forming a first encapsulant to encapsulate the interposers; removing the carrier; and disposing at least a semiconductor element on each of the interposers. By cutting the substrate first, good interposers can be selected and rearranged such that finished packages can be prevented from being wasted due to inferior interposers.

Abstract translation: 提供一种制造半导体封装的方法，包括：将衬底切割成多个中介层; 将所述插入件布置在载体的多个开口中，其中所述开口彼此间隔一定距离; 形成第一密封剂以封装所述插入件; 移除载体; 以及在每个所述插入件上设置至少一个半导体元件。 通过首先切割基板，可以选择和重新布置良好的插入件，从而可以防止由于不良插入件浪费完成的封装。