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    METHOD OF ERASING DATA IN NONVOLATILE MEMORY DEVICE, NONVOLATILE MEMORY DEVICE PERFORMING THE SAME AND MEMORY SYSTEM INCLUDING THE SAME
    16.
    发明申请
    METHOD OF ERASING DATA IN NONVOLATILE MEMORY DEVICE, NONVOLATILE MEMORY DEVICE PERFORMING THE SAME AND MEMORY SYSTEM INCLUDING THE SAME 有权

    公开(公告)号：US20210012840A1

    公开(公告)日：2021-01-14

    申请号：US17036387

    申请日：2020-09-29

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Won-Bo Shim ,  Sang-Wan Nam ,  Ji-Ho Cho

    IPC: G11C16/16 ,  G11C16/26 ,  G11C16/30 ,  G11C7/10 ,  G11C16/04

    Abstract: A nonvolatile memory device includes a memory cell region, a peripheral circuit region, a memory block in the memory cell region, a row decoder in the peripheral circuit region, and a control circuit in the peripheral circuit region. The memory cell region includes a first metal pad. The peripheral circuit region includes a second metal pad and is vertically connected to the memory cell region by the first metal pad and the second metal pad. The memory block includes memory cells stacked in a direction intersecting a substrate, and is divided into a plurality of sub-blocks configured to be erased independently. The row decoder selects the memory block by units of a sub-block. The control circuit receives a data erase command for a selected sub-block among the plurality of sub-blocks, performs a data read operation on at least one victim sub-block among the plurality of sub-blocks in response to the data erase command, selectively performs a soft program operation on the at least one victim sub-block based on a result of the data read operation, and performs a data erase operation on the selected sub-block after the data read operation is performed and the soft program operation is selectively performed.

    Nonvolatile memory device, vertical NAND flash memory device and SSD device including the same
    17.
    发明授权
    Nonvolatile memory device, vertical NAND flash memory device and SSD device including the same 有权

    公开(公告)号：US10804293B2

    公开(公告)日：2020-10-13

    申请号：US16440299

    申请日：2019-06-13

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sang-Won Park ,  Sang-Wan Nam ,  Bong-Soon Lim

    IPC: H01L27/11582 ,  G11C16/04 ,  G11C16/14 ,  G11C16/10 ,  G11C16/26 ,  H01L27/11573 ,  G06F3/06 ,  H01L27/1157 ,  H01L27/11565

    Abstract: A nonvolatile memory device includes a semiconductor substrate including a page buffer region, a memory cell array, bitlines, first vertical conduction paths, and second vertical conduction paths. The memory cell array is formed in a memory cell region above the semiconductor substrate and includes memory cells. The bitlines extend in a column direction above the memory cell array. Each of bitlines is cut into each of first bitline segments and each of second bitline segments. The first vertical conduction paths extend in a vertical direction and penetrate a column-directional central region of the memory cell region. The first vertical conduction paths connect the first bitline segments and the page buffer region. The second vertical conduction paths extend in the vertical direction and penetrate the column-directional central region. The second vertical conduction paths connect the second bitline segments and the page buffer region.

    Three-dimensional nonvolatile memory and related read method designed to reduce read disturbance
    18.
    发明授权
    Three-dimensional nonvolatile memory and related read method designed to reduce read disturbance 有权

    公开(公告)号：US10803947B2

    公开(公告)日：2020-10-13

    申请号：US16801214

    申请日：2020-02-26

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sang-Wan Nam ,  Won-Taeck Jung

    IPC: G11C16/04 ,  G11C16/34 ,  G11C16/24 ,  G11C16/26 ,  G11C16/08 ,  G11C16/10

    Abstract: A nonvolatile memory device performs a read operation comprising first and second intervals. In the first interval the device applies a turn-on voltage to string selection lines and ground selection lines connected to the string selection transistors and the ground selection transistors, respectively. In the second interval, the device applies a turn-off voltage to unselected string selection lines and unselected ground selection lines while continuing to apply the turn-on voltage to a selected string selection line and a selected ground selection line. In both the first and second intervals, the device applies a first read voltage to a selected wordline connected to memory cells to be read by the read operation and applying a second read voltage to unselected wordlines among connected to memory cells not to be read by the read operation.

    Nonvolatile memory device
    19.
    发明授权
    Nonvolatile memory device 有权

    公开(公告)号：US10777233B1

    公开(公告)日：2020-09-15

    申请号：US16590326

    申请日：2019-10-01

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sang-Wan Nam ,  Euihyun Cheon ,  Byungjun Min

    IPC: G11C5/06 ,  G11C16/16 ,  G11C7/18 ,  G11C16/30 ,  G11C16/08

    Abstract: A nonvolatile memory device includes a first memory block including a plurality of cell transistors interconnected with a plurality of ground selection lines, a plurality of word lines, and a plurality of string selection lines, which are stacked in a direction perpendicular to a substrate, a block selecting circuit that is connected with the plurality of ground selection lines, the plurality of word lines, and the plurality of string selection lines, and provides corresponding driving voltages to the plurality of ground selection lines, the plurality of word lines, and the plurality of string selection lines in response to a block selection signal, respectively, and a block unselecting circuit that is connected only with specific string selection lines of the plurality of string selection lines, and provides an off-voltage only to the specific string selection lines in response to a block un-selection signal.

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