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1.发明授权公开(公告)号：US10909032B2
公开(公告)日：2021-02-02
申请号：US16849645
申请日：2020-04-15
Applicant: Samsung Electronics Co., Ltd.
Inventor： Chi Weon Yoon , Dong Hyuk Chae , Sang-Wan Nam , Jung-Yun Yun
Abstract: At least one address scheduling method includes selecting a first bit line, selecting a first string connected to the first bit line, performing address scheduling on N pages of each of multi-level cells in the first string sequentially from a bottom word line to a top word line, and after completing the address scheduling on all word lines in the first string, performing address scheduling on second to k-th strings sequentially in the same manner as performed with respect to the first string, where “k” is 2 or a natural number greater than 2.
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公开(公告)号：US09881685B2
公开(公告)日：2018-01-30
申请号：US15461835
申请日：2017-03-17
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Chi Weon Yoon , Donghyuk Chae , Jae-Woo Park , Sang-Wan Nam
CPC classification number: G11C16/3445 , G11C16/0483 , G11C16/06 , G11C16/16 , H01L29/792
Abstract: A method of operating a non-volatile memory device includes performing an erasing operation to memory cells associated with a plurality of string selection lines (SSLs), the memory cells associated with the plurality of SSLs constituting a memory block, and verifying the erasing operation to second memory cells associated with a second SSL after verifying the erasing operation to first memory cells associated with a first SSL.
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公开(公告)号：US11737271B2
公开(公告)日：2023-08-22
申请号：US16993570
申请日：2020-08-14
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Tae-Hong Kwon , Chan Ho Kim , Kyung Hwa Yun , Dae Seok Byeon , Chi Weon Yoon
CPC classification number: H10B43/27 , G11C5/145 , G11C16/08 , G11C16/24 , G11C16/32 , H10B43/35 , H10B43/40
Abstract: In order to permit dense integration of a high number of stacked word lines in the semiconductor memory device, a charge pump is included in the semiconductor memory device. The charge pump makes use of a capacitor. The capacitor is implemented with respect to the dense integration. Some components are placed under the stacked word lines, and some are not under the stacked word lines. The capacity of the capacitor not under the stacked word lines is provided in part by a parallel structure.
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4.发明授权公开(公告)号：US10671529B2
公开(公告)日：2020-06-02
申请号：US15790583
申请日：2017-10-23
Applicant: Samsung Electronics Co., Ltd.
Inventor： Chi Weon Yoon , Dong Hyuk Chae , Sang-Wan Nam , Jung-Yun Yun
Abstract: At least one address scheduling method includes selecting a first bit line, selecting a first string connected to the first bit line, performing address scheduling on N pages of each of multi-level cells in the first string sequentially from a bottom word line to a top word line, and after completing the address scheduling on all word lines in the first string, performing address scheduling on second to k-th strings sequentially in the same manner as performed with respect to the first string, where “k” is 2 or a natural number greater than 2.
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公开(公告)号：US10181348B2
公开(公告)日：2019-01-15
申请号：US15677055
申请日：2017-08-15
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hyun Kook Park , Young Hoon Oh , Chi Weon Yoon , Yong Jun Lee , Chea Ouk Lim
Abstract: A resistive memory element or device includes: a first, main, memory cell area including a plurality of first resistive memory cells; and a second, buffer, memory cell area including a plurality of second resistive memory cells. The first resistive memory cells of the main memory cell area are configured to store data therein, and the second resistive memory cells of the buffer memory cell area are configured to temporarily store portions of the data therein for at least a stabilization time period while the portions of the data stabilize in the main memory cell area.
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Patent Agency Ranking
公开(公告)号：US09627086B2
公开(公告)日：2017-04-18
申请号：US14811380
申请日：2015-07-28
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Chi Weon Yoon , Donghyuk Chae , Jae-Woo Park , Sang-Wan Nam
Abstract: A method of operating a non-volatile memory device includes performing an erasing operation to memory cells associated with a plurality of string selection lines (SSLs), the memory cells associated with the plurality of SSLs constituting a memory block, and verifying the erasing operation to second memory cells associated with a second SSL after verifying the erasing operation to first memory cells associated with a first SSL.
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公开(公告)号：US12147340B2
公开(公告)日：2024-11-19
申请号：US18312109
申请日：2023-05-04
Applicant: Samsung Electronics Co., Ltd.
Inventor： Chi Weon Yoon , Dong Hyuk Chae , Sang-Wan Nam , Jung-Yun Yun
Abstract: At least one address scheduling method includes selecting a first bit line, selecting a first string connected to the first bit line, performing address scheduling on N pages of each of multi-level cells in the first string sequentially from a bottom word line to a top word line, and after completing the address scheduling on all word lines in the first string, performing address scheduling on second to k-th strings sequentially in the same manner as performed with respect to the first string, where “k” is 2 or a natural number greater than 2.
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公开(公告)号：US10748621B2
公开(公告)日：2020-08-18
申请号：US16111539
申请日：2018-08-24
Applicant: Samsung Electronics Co., Ltd.
Inventor： Dong Hun Kwak , Sang Wan Nam , Chi Weon Yoon
IPC: G11C16/10 , H01L27/11524 , G11C16/08 , H01L27/11556 , G11C16/14 , G11C16/34 , H01L27/1157 , H01L27/11582 , G11C16/04 , G11C16/26 , G11C11/56
Abstract: A memory device includes a memory cell array including a plurality of word lines, at least one select line provided above the plurality of word lines, and a channel region passing through the plurality of word lines and the at least one select line, the plurality of word lines and the channel region providing a plurality of memory cells, and a controller. The controller is to store data in a program memory cell among the plurality of memory cells by sequentially performing a first programming operation and a second programming operation, and to determine a program voltage input to a program word line connected to the program memory cell, in the first programming operation, based on information regarding the program memory cell.
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公开(公告)号：US09947416B2
公开(公告)日：2018-04-17
申请号：US14811380
申请日：2015-07-28
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Chi Weon Yoon , Donghyuk Chae , Jae-Woo Park , Sang-Wan Nam
IPC: G11C16/34 , G11C16/04 , G11C16/06 , G11C16/16 , H01L29/792
CPC classification number: G11C16/3445 , G11C16/0483 , G11C16/06 , G11C16/16 , H01L29/792
Abstract: A method of operating a non-volatile memory device includes performing an erasing operation to memory cells associated with a plurality of string selection lines (SSLs), the memory cells associated with the plurality of SSLs constituting a memory block, and verifying the erasing operation to second memory cells associated with a second SSL after verifying the erasing operation to first memory cells associated with a first SSL.
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公开(公告)号：US10340000B2
公开(公告)日：2019-07-02
申请号：US15795245
申请日：2017-10-26
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hyun Kook Park , Jung Sunwoo , Chi Weon Yoon
IPC: G11C13/00
Abstract: An operating method of a memory device is provided. Using a statistical model, a resistance Rdyn of a variable resistor of a memory cell and a variation ΔRdyn of the resistance Rdyn are determined. Based on the resistance Rdyn and the variation ΔRdyn of the resistance Rdyn, an average resistance Rdyn_avg and a beta value of the variable resistor are determined. Then, using the average resistance Rdyn_avg and the beta value, a resistance Ra of an insertion resistor, connected between the memory cell and a power supply generator for generating a power supply voltage VPGM, is determined.
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