公开(公告)号：US11170856B2

公开(公告)日：2021-11-09

申请号：US17113149

申请日：2020-12-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang Wan Nam ,  Yong Hyuk Choi ,  Jun Yong Park ,  Jung No Im

IPC: G11C11/34 ,  G11C16/14 ,  G11C16/26 ,  G11C7/10 ,  G11C16/04 ,  G06F12/02

Abstract: A memory device includes a first memory cell, and a second memory cell different from the first memory cell, wherein the first memory cell and the second memory cell are included in same memory block; a first word line connected to the first memory cell; a second word line, different from the first word line, connected to the second memory cell; an address decoder which applies one of an erase voltage and an inhibit voltage different from the erase voltage to each of the first and second word lines; and a control logic which controls an erasing operation on the memory block, using the address decoder, wherein while the erasing operation on the memory block is executed, the inhibit voltage is applied to the first word line after the erase voltage is applied, and the erase voltage is applied to the second word line after the inhibit voltage is applied.

公开(公告)号：US10892017B2

公开(公告)日：2021-01-12

申请号：US16508016

申请日：2019-07-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang Wan Nam ,  Yong Hyuk Choi ,  Jun Yong Park ,  Jung No Im

IPC: G11C11/34 ,  G11C16/14 ,  G11C16/26 ,  G11C7/10 ,  G11C16/04 ,  G06F12/02

Abstract: A memory device comprises: a first memory cell, and a second memory cell different from the first memory cell, wherein the first memory cell and the second memory cell are included in same memory block; a first word line connected to the first memory cell; a second word line, different from the first word line, connected to the second memory cell; an address decoder which applies one of an erase voltage and an inhibit voltage different from the erase voltage to each of the first and second word lines; and a control logic which controls an erasing operation on the memory block, using the address decoder, wherein while the erasing operation on the memory block is executed, the inhibit voltage is applied to the first word line after the erase voltage is applied, and the erase voltage is applied to the second word line after the inhibit voltage is applied.

公开(公告)号：US10964398B2

公开(公告)日：2021-03-30

申请号：US16983278

申请日：2020-08-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang Wan Nam ,  Yong Hyuk Choi ,  Jun Yong Park ,  Jung No Im

IPC: G11C11/34 ,  G11C16/16 ,  G11C16/32 ,  G11C16/30 ,  G11C16/08

Abstract: A memory device includes a memory cell region including a metal pad and first and second memory cells in a memory block, a peripheral circuit region including another metal pad and vertically connected to the memory cell region by the metal pads, a first word line in the memory cell region connected to the first memory cell, a second word line in the memory cell region connected to the second memory cell, an address decoder in the peripheral circuit region applying one of an erase voltage and an inhibit voltage to the first and second word lines, and control logic in the peripheral circuit region controlling an erasing operation on the memory block. During the erasing operation the inhibit voltage is applied to the first word line after the erase voltage, and the erase voltage is applied to the second word line after the inhibit voltage.

公开(公告)号：US10748621B2

公开(公告)日：2020-08-18

申请号：US16111539

申请日：2018-08-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong Hun Kwak ,  Sang Wan Nam ,  Chi Weon Yoon

IPC: G11C16/10 ,  H01L27/11524 ,  G11C16/08 ,  H01L27/11556 ,  G11C16/14 ,  G11C16/34 ,  H01L27/1157 ,  H01L27/11582 ,  G11C16/04 ,  G11C16/26 ,  G11C11/56

Abstract: A memory device includes a memory cell array including a plurality of word lines, at least one select line provided above the plurality of word lines, and a channel region passing through the plurality of word lines and the at least one select line, the plurality of word lines and the channel region providing a plurality of memory cells, and a controller. The controller is to store data in a program memory cell among the plurality of memory cells by sequentially performing a first programming operation and a second programming operation, and to determine a program voltage input to a program word line connected to the program memory cell, in the first programming operation, based on information regarding the program memory cell.

公开(公告)号：USRE50306E1

公开(公告)日：2025-02-18

申请号：US17666283

申请日：2022-02-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang Wan Nam ,  Yong Hyuk Choi ,  Jun Yong Park ,  Jung No Im

IPC: G11C11/34 ,  G06F12/02 ,  G11C7/10 ,  G11C16/04 ,  G11C16/14 ,  G11C16/26

Abstract: A memory device comprises: a first memory cell, and a second memory cell different from the first memory cell, wherein the first memory cell and the second memory cell are included in same memory block; a first word line connected to the first memory cell; a second word line, different from the first word line, connected to the second memory cell; an address decoder which applies one of an erase voltage and an inhibit voltage different from the erase voltage to each of the first and second word lines; and a control logic which controls an erasing operation on the memory block, using the address decoder, wherein while the erasing operation on the memory block is executed, the inhibit voltage is applied to the first word line after the erase voltage is applied, and the erase voltage is applied to the second word line after the inhibit voltage is applied. The present disclosure provides a memory device for detecting a word line bridge defect through erase verification of the memory device. The memory device comprises: a first memory cell and a second memory cell; a first word line connected to the first memory cell; a second word line connected to the second memory cell; an address decoder which is configured to apply one of an erase voltage and an inhibit voltage to each of the first and second word lines; and a control logic which is configured to control an erasing operation on the memory block, using the address decoder, wherein while the erasing operation on the memory block is executed, the inhibit voltage is applied to the first word line after the erase voltage is applied, and the erase voltage is applied to the second word line after the inhibit voltage is applied.

公开(公告)号：US11074978B2

公开(公告)日：2021-07-27

申请号：US16891455

申请日：2020-06-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong Hun Kwak ,  Sang Wan Nam ,  Chi Weon Yoon

IPC: G11C16/10 ,  H01L27/11524 ,  G11C16/08 ,  H01L27/11556 ,  G11C16/14 ,  G11C16/34 ,  H01L27/1157 ,  H01L27/11582 ,  G11C16/04 ,  G11C16/26 ,  G11C11/56

Abstract: A memory device includes a memory cell array including a plurality of word lines, at least one select line provided above the plurality of word lines, and a channel region passing through the plurality of word lines and the at least one select line, the plurality of word lines and the channel region providing a plurality of memory cells, and a controller. The controller is to store data in a program memory cell among the plurality of memory cells by sequentially performing a first programming operation and a second programming operation, and to determine a program voltage input to a program word line connected to the program memory cell, in the first programming operation, based on information regarding the program memory cell.

公开(公告)号：US10679702B2

公开(公告)日：2020-06-09

申请号：US16125905

申请日：2018-09-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong Hun Kwak ,  Sang Wan Nam ,  Chi Weon Yoon

IPC: G11C16/10 ,  H01L27/11556 ,  G11C16/26 ,  G11C16/04 ,  H01L27/11582

Abstract: A memory device includes a first memory area, a second memory area, a third memory area and a controller. The first memory area has a plurality of first memory cells sharing a first channel area. The second memory area has a plurality of second memory cells sharing the first channel area. The third memory area having a plurality of third memory cells sharing a second channel area, the second channel area being different from the first channel area, the first channel area and the second channel area being connected to a bit line. The controller is configured to input a voltage for the second memory cells to the second memory cells and a voltage for the third memory cells to the third memory cells, when a controlling operation is performed on the first memory cells, the voltages for the second and third memory cells having different magnitudes.

公开(公告)号：US10566039B2

公开(公告)日：2020-02-18

申请号：US16043474

申请日：2018-07-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang Wan Nam ,  Dong Hun Kwak ,  Wan Dong Kim ,  Chi Weon Yoon

IPC: G11C8/00 ,  G11C8/14 ,  H01L27/11582 ,  G11C16/26 ,  G11C16/14 ,  G11C16/08 ,  H01L27/1157

Abstract: A memory device includes a memory cell array including a plurality of word lines, a first string select line above the plurality of word lines, and a second string select line between the first string select line and the plurality of word lines, and a controller. During an operation of reading data of a first memory cell connected to a first word line among the plurality of word lines, the controller is to supply a first voltage to the first string select line and to supply a second voltage to the second string select line, the second voltage being greater than the first voltage.