公开(公告)号：US10892017B2

公开(公告)日：2021-01-12

申请号：US16508016

申请日：2019-07-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang Wan Nam ,  Yong Hyuk Choi ,  Jun Yong Park ,  Jung No Im

IPC: G11C11/34 ,  G11C16/14 ,  G11C16/26 ,  G11C7/10 ,  G11C16/04 ,  G06F12/02

Abstract: A memory device comprises: a first memory cell, and a second memory cell different from the first memory cell, wherein the first memory cell and the second memory cell are included in same memory block; a first word line connected to the first memory cell; a second word line, different from the first word line, connected to the second memory cell; an address decoder which applies one of an erase voltage and an inhibit voltage different from the erase voltage to each of the first and second word lines; and a control logic which controls an erasing operation on the memory block, using the address decoder, wherein while the erasing operation on the memory block is executed, the inhibit voltage is applied to the first word line after the erase voltage is applied, and the erase voltage is applied to the second word line after the inhibit voltage is applied.

公开(公告)号：USRE50306E1

公开(公告)日：2025-02-18

申请号：US17666283

申请日：2022-02-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang Wan Nam ,  Yong Hyuk Choi ,  Jun Yong Park ,  Jung No Im

IPC: G11C11/34 ,  G06F12/02 ,  G11C7/10 ,  G11C16/04 ,  G11C16/14 ,  G11C16/26

Abstract: A memory device comprises: a first memory cell, and a second memory cell different from the first memory cell, wherein the first memory cell and the second memory cell are included in same memory block; a first word line connected to the first memory cell; a second word line, different from the first word line, connected to the second memory cell; an address decoder which applies one of an erase voltage and an inhibit voltage different from the erase voltage to each of the first and second word lines; and a control logic which controls an erasing operation on the memory block, using the address decoder, wherein while the erasing operation on the memory block is executed, the inhibit voltage is applied to the first word line after the erase voltage is applied, and the erase voltage is applied to the second word line after the inhibit voltage is applied. The present disclosure provides a memory device for detecting a word line bridge defect through erase verification of the memory device. The memory device comprises: a first memory cell and a second memory cell; a first word line connected to the first memory cell; a second word line connected to the second memory cell; an address decoder which is configured to apply one of an erase voltage and an inhibit voltage to each of the first and second word lines; and a control logic which is configured to control an erasing operation on the memory block, using the address decoder, wherein while the erasing operation on the memory block is executed, the inhibit voltage is applied to the first word line after the erase voltage is applied, and the erase voltage is applied to the second word line after the inhibit voltage is applied.

公开(公告)号：US11170856B2

公开(公告)日：2021-11-09

申请号：US17113149

申请日：2020-12-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang Wan Nam ,  Yong Hyuk Choi ,  Jun Yong Park ,  Jung No Im

IPC: G11C11/34 ,  G11C16/14 ,  G11C16/26 ,  G11C7/10 ,  G11C16/04 ,  G06F12/02

Abstract: A memory device includes a first memory cell, and a second memory cell different from the first memory cell, wherein the first memory cell and the second memory cell are included in same memory block; a first word line connected to the first memory cell; a second word line, different from the first word line, connected to the second memory cell; an address decoder which applies one of an erase voltage and an inhibit voltage different from the erase voltage to each of the first and second word lines; and a control logic which controls an erasing operation on the memory block, using the address decoder, wherein while the erasing operation on the memory block is executed, the inhibit voltage is applied to the first word line after the erase voltage is applied, and the erase voltage is applied to the second word line after the inhibit voltage is applied.

公开(公告)号：US10964398B2

公开(公告)日：2021-03-30

申请号：US16983278

申请日：2020-08-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang Wan Nam ,  Yong Hyuk Choi ,  Jun Yong Park ,  Jung No Im

IPC: G11C11/34 ,  G11C16/16 ,  G11C16/32 ,  G11C16/30 ,  G11C16/08

Abstract: A memory device includes a memory cell region including a metal pad and first and second memory cells in a memory block, a peripheral circuit region including another metal pad and vertically connected to the memory cell region by the metal pads, a first word line in the memory cell region connected to the first memory cell, a second word line in the memory cell region connected to the second memory cell, an address decoder in the peripheral circuit region applying one of an erase voltage and an inhibit voltage to the first and second word lines, and control logic in the peripheral circuit region controlling an erasing operation on the memory block. During the erasing operation the inhibit voltage is applied to the first word line after the erase voltage, and the erase voltage is applied to the second word line after the inhibit voltage.

公开(公告)号：US10394064B2

公开(公告)日：2019-08-27

申请号：US15726614

申请日：2017-10-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyun Yong Choi ,  Ha Na Kim ,  Jun Yong Park ,  Jee Hoon Park ,  You Na Choo ,  Soo Hyun Whang ,  Gyu Sung Do

IPC: H05K9/00 ,  G02F1/1333 ,  G02F1/1335

Abstract: A display apparatus is provided. The display apparatus includes a display panel that displays an image in a forward direction thereof; a bezel disposed on an edge of the display panel; and a light refraction member disposed in front of the bezel, the light refraction member including a transparent material, and refracting light of an outer rear side of the bezel in a forward direction of the bezel.