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    MEMORY DEVICE, MEMORY SYSTEM, METHOD OF OPERATING THE MEMORY DEVICE, AND METHOD OF OPERATING THE MEMORY SYSTEM
    1.
    发明申请
    MEMORY DEVICE, MEMORY SYSTEM, METHOD OF OPERATING THE MEMORY DEVICE, AND METHOD OF OPERATING THE MEMORY SYSTEM 有权
    存储器件，存储器系统，操作存储器件的方法和操作存储器系统的方法

    公开(公告)号：US20170069389A1

    公开(公告)日：2017-03-09

    申请号：US15251090

    申请日：2016-08-30

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： SANG-SOO PARK ,  Yoon Kim ,  Won-Bo Shim

    IPC: G11C16/14 ,  G11C16/08 ,  G11C16/34 ,  G11C16/04

    CPC classification number: G11C16/14 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/32 ,  G11C16/349

    Abstract: A method of erasing a non-volatile memory device which includes a plurality of NAND strings is provided as follows. A first voltage is applied to each of word lines for a corresponding effective erasing execution time. An erase operation is performed on memory cells connected to each of the word lines for the corresponding effective erasing execution time. A second voltage is applied to each of at least some word lines among the word lines for a corresponding erasing-prohibited time after the corresponding effective erasing execution time elapses. A sum of the corresponding effective erasing execution time and the corresponding erasing-prohibited time for each of the at least some word lines is substantially equal to an erasure interval during which an erase operation is performed using the first voltage and the second voltage higher than the first voltage. The word lines are stacked on a substrate.

    Abstract translation: 如下提供擦除包括多个NAND串的非易失性存储器件的方法。 对每个字线施加第一电压用于相应的有效擦除执行时间。 对连接到每个字线的存储器单元执行相应的有效擦除执行时间的擦除操作。 在相应的有效擦除执行时间过去之后，对于相应的擦除禁止时间，在字线中的至少一些字线中的每一个上施加第二电压。 对于至少一些字线中的每一个，对应的有效擦除执行时间和相应的擦除禁止时间的总和基本上等于使用第一电压和第二电压高于第二电压的第二电压执行擦除操作的擦除间隔 第一电压。 字线堆叠在基板上。

    Method of erasing data in nonvolatile memory device, nonvolatile memory device performing the same and memory system including the same
    3.
    发明授权
    Method of erasing data in nonvolatile memory device, nonvolatile memory device performing the same and memory system including the same 有权

    公开(公告)号：US11056194B2

    公开(公告)日：2021-07-06

    申请号：US17036387

    申请日：2020-09-29

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Won-Bo Shim ,  Sang-Wan Nam ,  Ji-Ho Cho

    IPC: G11C16/16 ,  G11C16/26 ,  G11C16/30 ,  G11C7/10 ,  G11C16/04 ,  G11C8/14

    Abstract: A nonvolatile memory device includes a memory cell region, a peripheral circuit region, a memory block in the memory cell region, a row decoder in the peripheral circuit region, and a control circuit in the peripheral circuit region. The memory cell region includes a first metal pad. The peripheral circuit region includes a second metal pad and is vertically connected to the memory cell region by the first metal pad and the second metal pad. The memory block includes memory cells stacked in a direction intersecting a substrate, and is divided into a plurality of sub-blocks configured to be erased independently. The row decoder selects the memory block by units of a sub-block. The control circuit receives a data erase command for a selected sub-block among the plurality of sub-blocks, performs a data read operation on at least one victim sub-block among the plurality of sub-blocks in response to the data erase command, selectively performs a soft program operation on the at least one victim sub-block based on a result of the data read operation, and performs a data erase operation on the selected sub-block after the data read operation is performed and the soft program operation is selectively performed.

    METHOD OF ERASING DATA IN NONVOLATILE MEMORY DEVICE, NONVOLATILE MEMORY DEVICE PERFORMING THE SAME AND MEMORY SYSTEM INCLUDING THE SAME
    5.
    发明申请
    METHOD OF ERASING DATA IN NONVOLATILE MEMORY DEVICE, NONVOLATILE MEMORY DEVICE PERFORMING THE SAME AND MEMORY SYSTEM INCLUDING THE SAME 有权

    公开(公告)号：US20210012840A1

    公开(公告)日：2021-01-14

    申请号：US17036387

    申请日：2020-09-29

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Won-Bo Shim ,  Sang-Wan Nam ,  Ji-Ho Cho

    IPC: G11C16/16 ,  G11C16/26 ,  G11C16/30 ,  G11C7/10 ,  G11C16/04

    Abstract: A nonvolatile memory device includes a memory cell region, a peripheral circuit region, a memory block in the memory cell region, a row decoder in the peripheral circuit region, and a control circuit in the peripheral circuit region. The memory cell region includes a first metal pad. The peripheral circuit region includes a second metal pad and is vertically connected to the memory cell region by the first metal pad and the second metal pad. The memory block includes memory cells stacked in a direction intersecting a substrate, and is divided into a plurality of sub-blocks configured to be erased independently. The row decoder selects the memory block by units of a sub-block. The control circuit receives a data erase command for a selected sub-block among the plurality of sub-blocks, performs a data read operation on at least one victim sub-block among the plurality of sub-blocks in response to the data erase command, selectively performs a soft program operation on the at least one victim sub-block based on a result of the data read operation, and performs a data erase operation on the selected sub-block after the data read operation is performed and the soft program operation is selectively performed.

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