公开(公告)号：US10985103B2

公开(公告)日：2021-04-20

申请号：US16577591

申请日：2019-09-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joon Goo Hong ,  Rwik Sengupta

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/50 ,  H01L23/522 ,  H01L23/532

Abstract: An integrated circuit (IC) apparatus and a method of forming a conductive material in a backside of an IC are provided. The IC apparatus includes a substrate including a frontside and a backside; at least one first insulating material deposited in the backside of the substrate in a form of a trench; a conductive material deposited in each of the at least one first insulating material; at least one second insulating material deposited on the conductive material to insulate the conductive material from the substrate; an epitaxial crystalline material grown on the frontside of the substrate; at least one semiconductor component formed in the epitaxial crystalline material; and at least one via formed in the substrate to connect the conductive material to the at least one semiconductor component.

公开(公告)号：US10910313B2

公开(公告)日：2021-02-02

申请号：US15948543

申请日：2018-04-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Rwik Sengupta ,  Mark Rodder ,  Joon Goo Hong ,  Titash Rakshit

IPC: H01L27/088 ,  H01L23/535 ,  H01L23/528 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/78

Abstract: An integrated circuit including a series of field effect transistors. Each field effect transistor includes a source region, a drain region, a channel region extending between the source region and the drain region, a gate on the channel region, a gate contact on the gate at an active region of the gate, a source contact on the source region, and a drain contact on the drain region. Upper surfaces of the source and drain contacts are spaced below an upper surface of the gate by a depth.

公开(公告)号：US20200279811A1

公开(公告)日：2020-09-03

申请号：US16577591

申请日：2019-09-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joon Goo Hong ,  Rwik Sengupta

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/50 ,  H01L23/522 ,  H01L23/532

Abstract: An integrated circuit (IC) apparatus and a method of forming a conductive material in a backside of an IC are provided. The IC apparatus includes a substrate including a frontside and a backside; at least one first insulating material deposited in the backside of the substrate in a form of a trench; a conductive material deposited in each of the at least one first insulating material; at least one second insulating material deposited on the conductive material to insulate the conductive material from the substrate; an epitaxial crystalline material grown on the frontside of the substrate; at least one semiconductor component formed in the epitaxial crystalline material; and at least one via formed in the substrate to connect the conductive material to the at least one semiconductor component.

公开(公告)号：US20190318998A1

公开(公告)日：2019-10-17

申请号：US16453475

申请日：2019-06-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Harsono S. Simka ,  Ganesh Hegde ,  Joon Goo Hong ,  Rwik Sengupta ,  Mark S. Rodder

IPC: H01L23/00 ,  H01L23/522 ,  H01L27/02

Abstract: A hardware-embedded security system is described. The system includes connective components, circuit elements and an insulator. The connective components include a variable conductivity layer that is conductive for a first stoichiometry and insulating for a second stoichiometry. A first portion of the circuit elements are connected to a first portion of the connective components and are active. A the second portion of the circuit elements are connected to a second portion of the connective components and are inactive. The insulator is adjacent to at least a portion of each of the connective components. The first stoichiometry is indistinguishable from the second stoichiometry via optical imaging and electron imaging of a portion of the insulator and the variable conductivity layer.

公开(公告)号：US20180254350A1

公开(公告)日：2018-09-06

申请号：US15656898

申请日：2017-07-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ryan M. Hatcher ,  Rwik Sengupta ,  Chris Bowen

IPC: H01L29/78 ,  H03K19/20 ,  H01L27/11

CPC classification number: H01L29/78391 ,  H01L27/1104 ,  H03K19/20

Abstract: A system of unipolar digital logic. Ferroelectric field effect transistors having channels of a first polarity, are combined, in circuits, with simple field effect transistors having channels of the same polarity, to form logic gates and/or memory cells.

公开(公告)号：US09768062B1

公开(公告)日：2017-09-19

申请号：US15276748

申请日：2016-09-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jorge A. Kittl ,  David Seo ,  Kota Oikawa ,  Kim Changhwa ,  Rwik Sengupta ,  Mark S. Rodder

IPC: H01L21/44 ,  H01L21/768

CPC classification number: H01L21/76879 ,  H01L21/28518 ,  H01L21/76846 ,  H01L21/76855 ,  H01L21/76897 ,  H01L23/485 ,  H01L29/785

Abstract: A method for forming a low parasitic capacitance contact to a source-drain structure of a fin field effect transistor device. In some embodiments the method includes etching a long trench down to the source-drain structure, the trench being sufficiently long to extend across all the of source-drain regions of the device. A conductive layer is formed on the source-drain structure, and the trench is filled with a first fill material. A second, narrower trench is opened along a portion of the length of the first trench, and filled with a second fill material. The first fill material may be conductive, and may form the contact. If the first fill material is not conductive, a third trench may be opened, in the portion of the first trench not filled with the second fill material, and filled with a conductive material, to form the contact.

公开(公告)号：US20170098661A1

公开(公告)日：2017-04-06

申请号：US15210867

申请日：2016-07-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Titash Rakshit ,  Borna J. Obradovic ,  Rwik Sengupta ,  Wei-E Wang ,  Ryan Hatcher ,  Mark S. Rodder

IPC: H01L27/12 ,  H01L23/528 ,  H01L29/24 ,  H01L29/10 ,  H01L29/78 ,  H01L29/423 ,  H01L29/66 ,  H01L21/84 ,  H01L23/522 ,  H01L29/45

CPC classification number: H01L27/12 ,  H01L21/84 ,  H01L23/5226 ,  H01L23/5228 ,  H01L23/528 ,  H01L29/1033 ,  H01L29/24 ,  H01L29/42376 ,  H01L29/45 ,  H01L29/66969 ,  H01L29/78 ,  H01L29/78681

Abstract: A semiconductor device includes a series of metal routing layers and a complementary pair of planar field-effect transistors (FETs) on an upper metal routing layer of the metal routing layers. The upper metal routing layer is M3 or higher. Each of the FETs includes a channel region of a crystalline material. The crystalline material may include one or more transition metal dichalcogenide materials such as MoS2, WS2, WSe2, and/or combinations thereof.

公开(公告)号：US11727258B2

公开(公告)日：2023-08-15

申请号：US17939807

申请日：2022-09-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Borna J. Obradovic ,  Titash Rakshit ,  Rwik Sengupta ,  Joon Goo Hong ,  Ryan M. Hatcher ,  Jorge A. Kittl ,  Mark S. Rodder

IPC: G06N3/063 ,  H01L29/423 ,  H01L29/78 ,  H01L21/28

CPC classification number: G06N3/063 ,  H01L29/40111 ,  H01L29/42392 ,  H01L29/785 ,  H01L29/78391

Abstract: A neuromorphic multi-bit digital weight cell configured to store a series of potential weights for a neuron in an artificial neural network. The neuromorphic multi-bit digital weight cell includes a parallel cell including a series of passive resistors in parallel and a series of gating transistors. Each gating transistor of the series of gating transistors is in series with one passive resistor of the series of passive resistors. The neuromorphic cell also includes a series of programming input lines connected to the series of gating transistors, an input terminal connected to the parallel cell, and an output terminal connected to the parallel cell.

公开(公告)号：US20230004789A1

公开(公告)日：2023-01-05

申请号：US17939807

申请日：2022-09-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Borna J. Obradovic ,  Titash Rakshit ,  Rwik Sengupta ,  Joon Goo Hong ,  Ryan M. Hatcher ,  Jorge A. Kittl ,  Mark S. Rodder

IPC: G06N3/063

Abstract: A neuromorphic multi-bit digital weight cell configured to store a series of potential weights for a neuron in an artificial neural network. The neuromorphic multi-bit digital weight cell includes a parallel cell including a series of passive resistors in parallel and a series of gating transistors. Each gating transistor of the series of gating transistors is in series with one passive resistor of the series of passive resistors. The neuromorphic cell also includes a series of programming input lines connected to the series of gating transistors, an input terminal connected to the parallel cell, and an output terminal connected to the parallel cell.

公开(公告)号：US11189692B2

公开(公告)日：2021-11-30

申请号：US16711582

申请日：2019-12-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung Ho Do ,  Rwik Sengupta

IPC: H01L27/24 ,  H01L29/06 ,  H01L29/08 ,  H01L29/78

Abstract: A cell architecture for vertical field-effect transistors (VFETs) is provided. The cell architecture includes: top source/drain (S/D) contact structure having a square shape in a plan view; and horizontal metal patterns formed on the top S/D contact structures and extended in an X-direction to be connected to a vertical pattern through with an output signal of a logic circuit formed by the VFETs. The cell architecture further includes a gate contact structure formed on a gate connection pattern connecting gates of the VFETs, wherein a super via is formed on the gate contact structure to receive an input signal of the logic circuit.