公开(公告)号：US20180076127A1

公开(公告)日：2018-03-15

申请号：US15816243

申请日：2017-11-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongmin Baek ,  Sangho Rha ,  Sanghoon Ahn ,  Wookyung You ,  Naein Lee

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L23/528 ,  H01L21/7682 ,  H01L21/76834 ,  H01L23/5222 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor devices are provided. A semiconductor device includes gaps between conductive patterns. Moreover, the semiconductor device includes a permeable layer on the conductive patterns. Methods of fabricating semiconductor devices are also provided.

公开(公告)号：US09576848B2

公开(公告)日：2017-02-21

申请号：US14847130

申请日：2015-09-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taejin Yim ,  Thomas Oszinda ,  Byunghee Kim ,  Sanghoon Ahn ,  Naein Lee ,  Keeyoung Jun

IPC: H01L21/76 ,  H01L21/768 ,  H01L21/02

CPC classification number: H01L21/76837 ,  H01L21/02126 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02203 ,  H01L21/02216 ,  H01L21/02222 ,  H01L21/02271 ,  H01L21/0231 ,  H01L21/02337 ,  H01L21/02359 ,  H01L21/02362 ,  H01L21/3105 ,  H01L21/76814 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76831 ,  H01L21/76843

Abstract: A method of treating a porous dielectric layer includes preparing a substrate on which the porous dielectric layer including an opening and pores exposed by the opening is formed, supplying a first precursor onto the substrate to form a first sub-sealing layer sealing the exposed pores, and supplying a second precursor onto the first sub-sealing layer to form a second sub-sealing layer covering the first sub-sealing layer. Each of the first and second precursors includes silicon, and a molecular weight of the second precursor is smaller than that of the first precursor.

Abstract translation: 一种处理多孔电介质层的方法包括制备其上形成有开口的多孔介电层和由该开口暴露的孔的基板，将第一前体供应到基板上以形成密封暴露孔的第一副密封层， 以及将第二前体供应到所述第一子密封层上以形成覆盖所述第一子密封层的第二副密封层。 第一和第二前体中的每一个包括硅，并且第二前体的分子量小于第一前体的分子量。

公开(公告)号：US09524937B2

公开(公告)日：2016-12-20

申请号：US14503877

申请日：2014-10-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongmin Baek ,  Sangho Rha ,  Sanghoon Ahn ,  Wookyung You ,  Naein Lee

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L23/528 ,  H01L21/7682 ,  H01L21/76834 ,  H01L23/5222 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor devices are provided. A semiconductor device includes gaps between conductive patterns. Moreover, the semiconductor device includes a permeable layer on the conductive patterns. Methods of fabricating semiconductor devices are also provided.

Abstract translation: 提供半导体器件。 半导体器件包括导电图案之间的间隙。 此外，半导体器件在导电图案上包括可渗透层。 还提供了制造半导体器件的方法。

公开(公告)号：US20150155233A1

公开(公告)日：2015-06-04

申请号：US14490964

申请日：2014-09-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyu-Hee Han ,  Pil-Kyu Kang ,  Taejin Yim ,  Naein Lee

IPC: H01L23/522 ,  H01L21/768

CPC classification number: H01L21/76879 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present inventive concepts provide semiconductor devices and methods for fabricating the same. The method includes forming an inter-metal dielectric layer including a plurality of dielectric layers on a substrate, forming a via-hole vertically penetrating the inter-metal dielectric layer and the substrate, providing carbon to at least one surface, such as a surface including carbon in the plurality of dielectric layers exposed by the via-hole, forming a via-dielectric layer covering an inner surface of the via-hole, and forming a through-electrode surrounded by the via-dielectric layer in the via-hole.

Abstract translation: 本发明构思提供半导体器件及其制造方法。 该方法包括在基板上形成包括多个电介质层的金属间介电层，形成垂直贯穿金属间介电层和基板的通孔，向至少一个表面提供碳，例如包括 通过通孔露出的多个电介质层中的碳，形成覆盖通路孔的内表面的通孔电介质层，以及形成由通路孔中的通孔电介质层包围的贯通电极。

公开(公告)号：US09972528B2

公开(公告)日：2018-05-15

申请号：US15374053

申请日：2016-12-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： VietHa Nguyen ,  Thomas Oszinda ,  Jongmin Baek ,  Sanghoon Ahn ,  Byunghee Kim ,  Wookyung You ,  Naein Lee

IPC: H01L29/00 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/7682 ,  H01L21/76802 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295

Abstract: A semiconductor device may include a substrate, a first interlayered insulating layer on the substrate having openings, conductive patterns provided in the openings, first to fourth insulating patterns stacked on the substrate provided with the conductive patterns, and a second interlayered insulating layer provided on the fourth insulating pattern.

公开(公告)号：US20180108540A1

公开(公告)日：2018-04-19

申请号：US15636849

申请日：2017-06-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae-Hyun Phee ,  Ho-Jin Lee ,  Taeseong Kim ,  Kwangjin Moon ,  Jin Ho An ,  Naein Lee

IPC: H01L21/48 ,  H01L23/498 ,  H01L21/683 ,  H01L23/64 ,  H01L23/00 ,  H05K3/40 ,  H05K1/16

CPC classification number: H01L21/486 ,  H01L21/6835 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/544 ,  H01L23/642 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L24/81 ,  H01L2223/54426 ,  H01L2224/13101 ,  H01L2224/16227 ,  H01L2224/48227 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/14511 ,  H01L2924/1461 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/37001 ,  H05K1/162 ,  H05K3/4038 ,  H01L2924/014 ,  H01L2224/45099

Abstract: A method of manufacturing a semiconductor package including forming a photoresist pattern on a first surface of an interposer substrate. The interposer substrate includes an electrode zone and a scribe line zone. The interposer substrate is etched using the photoresist pattern as a mask to form a first opening and a second opening respectively on the electrode zone and the scribe line zone. An insulation layer and a conductive layer are formed on the first surface of the interposer substrate. A width of the second opening is smaller than a width of the first opening. The insulation layer contacts each of the first surface of the interposer substrate, an inner surface of the first opening, and an inner surface of the second opening.

公开(公告)号：US09748170B2

公开(公告)日：2017-08-29

申请号：US15146112

申请日：2016-05-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangho Rha ,  Jongmin Baek ,  Wookyung You ,  Sanghoon Ahn ,  Naein Lee

IPC: H01L23/00 ,  H01L23/522 ,  H01L23/532 ,  H01L23/528 ,  H01L21/768 ,  H01L21/764

CPC classification number: H01L23/5226 ,  H01L21/764 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/7682 ,  H01L21/76837 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/5222 ,  H01L23/528 ,  H01L23/53223 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/00 ,  H01L2924/0002

Abstract: A semiconductor device includes a substrate, a plurality of first conductive patterns disposed on the substrate and a plurality of second conductive patterns disposed on the first conductive patterns. Respective air gaps are disposed between adjacent ones of the first conductive patterns overlying a first region of the substrate, while adjacent ones of the first conductive patterns overlying a second region of the substrate do not have air gaps disposed therebetween. The air gaps may include first air gaps, and the device may further include second air gaps disposed between adjacent ones of the second conductive patterns in the second region. Adjacent ones of the second conductive patterns overlying a second region of the substrate may not have air gaps disposed therebetween.

公开(公告)号：US20170092769A1

公开(公告)日：2017-03-30

申请号：US15374093

申请日：2016-12-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Donghyun Roh ,  Pankwi Park ,  Dongsuk Shin ,  Chulwoong Lee ,  Naein Lee

IPC: H01L29/78 ,  H01L21/762 ,  H01L21/306 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L29/7849 ,  H01L21/30604 ,  H01L21/76224 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823468 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/161 ,  H01L29/165 ,  H01L29/42376 ,  H01L29/66477 ,  H01L29/66553 ,  H01L29/7848

Abstract: According to embodiments of the inventive concept, a gate electrode is formed on a substrate, and a first spacer, a second spacer, and a third spacer are sequentially formed on a sidewall of the gate electrode. The substrate is etched to form a recess region. A compressive stress pattern is formed in the recess region. A protective spacer is formed on a sidewall of the third spacer. When the recess region is formed, a lower portion of the second spacer is removed to form a gap region between the first and third spacers. The protective spacer fills the gap region.

公开(公告)号：US20160148837A1

公开(公告)日：2016-05-26

申请号：US14847130

申请日：2015-09-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taejin Yim ,  Thomas Oszinda ,  Byunghee Kim ,  Sanghoon Ahn ,  Naein Lee ,  Keeyoung Jun

IPC: H01L21/768 ,  H01L21/02

CPC classification number: H01L21/76837 ,  H01L21/02126 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02203 ,  H01L21/02216 ,  H01L21/02222 ,  H01L21/02271 ,  H01L21/0231 ,  H01L21/02337 ,  H01L21/02359 ,  H01L21/02362 ,  H01L21/3105 ,  H01L21/76814 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76831 ,  H01L21/76843

Abstract: A method of treating a porous dielectric layer includes preparing a substrate on which the porous dielectric layer including an opening and pores exposed by the opening is formed, supplying a first precursor onto the substrate to form a first sub-sealing layer sealing the exposed pores, and supplying a second precursor onto the first sub-sealing layer to form a second sub-sealing layer covering the first sub-sealing layer. Each of the first and second precursors includes silicon, and a molecular weight of the second precursor is smaller than that of the first precursor.

Abstract translation: 一种处理多孔电介质层的方法包括制备其上形成有开口的多孔介电层和由该开口暴露的孔的基板，将第一前体供应到基板上以形成密封暴露孔的第一副密封层， 以及将第二前体供应到所述第一子密封层上以形成覆盖所述第一子密封层的第二副密封层。 第一和第二前体中的每一个包括硅，并且第二前体的分子量小于第一前体的分子量。

公开(公告)号：US09299836B2

公开(公告)日：2016-03-29

申请号：US14626211

申请日：2015-02-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong Hyuk Kim ,  Hoi Sung Chung ,  Dongsuk Shin ,  Naein Lee

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L29/165 ,  H01L29/04

CPC classification number: H01L29/7833 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66477 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

Abstract: A semiconductor device including source drain stressors and methods of manufacturing the same are provided. The methods may include forming a recess region in the substrate at a side of a gate pattern, and an inner surface of the recess region may include a first surface of a (100) crystal plane and a second surface of one of {111} crystal planes. The method may further include performing a first selective epitaxial growth (SEG) process to form a base epitaxial pattern on the inner surface of the recess region at a process pressure in a range of about 50 Torr to about 300 Torr. The method may also include performing a second selective epitaxial growth (SEG) process to form a bulk epitaxial pattern on the base epitaxial pattern.

Abstract translation: 提供了包括源漏应力源的半导体器件及其制造方法。 所述方法可以包括在栅极图案侧的基板中形成凹陷区域，并且凹部区域的内表面可以包括（100）晶面的第一表面和{111}晶体之一的第二表面 飞机 该方法还可以包括执行第一选择性外延生长（SEG）工艺，以在约50托至约300托的范围内的工艺压力下在凹陷区的内表面上形成基底外延图案。 该方法还可以包括执行第二选择性外延生长（SEG）工艺以在基底外延图案上形成体外延图案。