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    Methods of forming a semiconductor layer including germanium with low defectivity
    14.
    发明授权
    Methods of forming a semiconductor layer including germanium with low defectivity 有权
    形成低缺陷锗的半导体层的方法

    公开(公告)号：US09406508B2

    公开(公告)日：2016-08-02

    申请号：US14480869

    申请日：2014-09-09

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jorge A. Kittl ,  Mark S. Rodder

    IPC: H01L21/02 ,  H01L21/20

    CPC classification number: H01L21/02664 ,  H01L21/02488 ,  H01L21/02505 ,  H01L21/02532

    Abstract: Methods of forming a semiconductor layer including germanium with low defectivity are provided. The methods may include sequentially forming a silicate glass layer, a diffusion barrier layer including nitride and an interfacial layer including oxide on a substrate. The methods may also include forming a first semiconductor layer on the interfacial layer and converting a portion of the first semiconductor layer into a second semiconductor layer having a germanium concentration therein that is higher than a germanium concentration of the first semiconductor layer.

    Abstract translation: 提供了形成具有低缺陷度的锗的半导体层的方法。 所述方法可以包括依次形成硅酸盐玻璃层，包含氮化物的扩散阻挡层和在衬底上包含氧化物的界面层。 所述方法还可以包括在界面层上形成第一半导体层，并将第一半导体层的一部分转换成其锗浓度高于第一半导体层的锗浓度的第二半导体层。

    INTERFACE LAYER FOR GATE STACK USING 03 POST TREATMENT
    16.
    发明申请
    INTERFACE LAYER FOR GATE STACK USING 03 POST TREATMENT 有权
    接口层使用03后处理

    公开(公告)号：US20160042956A1

    公开(公告)日：2016-02-11

    申请号：US14666770

    申请日：2015-03-24

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jorge A. Kittl ,  Mark S. Rodder ,  Wei-E Wang

    IPC: H01L21/28 ,  H01L29/51 ,  H01L29/778

    CPC classification number: H01L29/513 ,  H01L21/28185 ,  H01L21/28194 ,  H01L29/517 ,  H01L29/778

    Abstract: Exemplary embodiments provide for fabricating a field effect transistor (FET) with an interface layer for a gate stack using an O3 post treatment. Aspects of the exemplary embodiments include: forming a semiconductor body upon a substrate; cleaning the surface of the semiconductor body; depositing a first dielectric layer on the semiconductor body; performing an O3 treatment that mixes with and penetrates the first dielectric layer and reacts with the semiconductor body to form a new interface layer; and performing gate stack processing, including deposition of a gate electrode.

    Abstract translation: 示例性实施例提供使用O3后处理来制造具有用于栅极堆叠的界面层的场效应晶体管（FET）。 示例性实施例的方面包括：在衬底上形成半导体本体; 清洁半导体体的表面; 在所述半导体主体上沉积第一电介质层; 执行与第一电介质层混合并渗透第一电介质层并与半导体本体反应以形成新界面层的O3处理; 以及执行栅堆叠处理，包括沉积栅电极。

    METHODS OF FABRICATING QUANTUM WELL FIELD EFFECT TRANSISTORS HAVING MULTIPLE DELTA DOPED LAYERS
    18.
    发明申请
    METHODS OF FABRICATING QUANTUM WELL FIELD EFFECT TRANSISTORS HAVING MULTIPLE DELTA DOPED LAYERS 有权
    制备具有多层掺杂层的量子阱效应晶体管的方法

    公开(公告)号：US20140329374A1

    公开(公告)日：2014-11-06

    申请号：US13947239

    申请日：2013-07-22

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Mark S. Rodder ,  Robert C. Bowen

    IPC: H01L29/66

    CPC classification number: H01L29/66469 ,  H01L29/66795 ,  H01L29/7784 ,  H01L29/785

    Abstract: Methods of fabricating quantum well field effect transistors are provided. The methods may include forming a first barrier layer including a first delta doped layer on a quantum well layer and forming a second barrier layer including a second delta doped layer selectively on a portion of the first barrier layer in a first region of the substrate. The methods may also include patterning the first and second barrier layers and the quantum well layer to form a first quantum well channel structure in the first region and patterning the first barrier layer and the quantum well layer to form a second quantum well channel structure in a second region. The methods may further include forming a gate insulating layer on the first and second quantum well channel structures of the substrate and forming a gate electrode layer on the gate insulating layer.

    Abstract translation: 提供了量子阱场效应晶体管的制造方法。 所述方法可以包括在量子阱层上形成包括第一δ掺杂层的第一势垒层，并且在衬底的第一区域中在第一势垒层的一部分上选择性地形成包括第二δ掺杂层的第二阻挡层。 所述方法还可以包括图案化第一和第二阻挡层和量子阱层，以在第一区域中形成第一量子阱沟道结构，并且对第一势垒层和量子阱层进行构图以形成第二量子阱沟道结构 第二区。 该方法还可以包括在衬底的第一和第二量子阱沟道结构上形成栅极绝缘层，并在栅极绝缘层上形成栅极电极层。

    METHODS OF FABRICATING INTEGRATED CIRCUIT DEVICE WITH FIN TRANSISTORS HAVING DIFFERENT THRESHOLD VOLTAGES
    19.
    发明申请
    METHODS OF FABRICATING INTEGRATED CIRCUIT DEVICE WITH FIN TRANSISTORS HAVING DIFFERENT THRESHOLD VOLTAGES 有权
    用具有不同阈值电压的晶体管制造集成电路器件的方法

    公开(公告)号：US20140273378A1

    公开(公告)日：2014-09-18

    申请号：US13801367

    申请日：2013-03-13

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Mark S. Rodder

    IPC: H01L29/66

    CPC classification number: H01L29/66795 ,  H01L21/823821 ,  H01L21/845

    Abstract: Methods of fabricating integrated circuit device with fin transistors having different threshold voltages are provided. The methods may include forming first and second semiconductor fins including first and second semiconductor materials, respectively, and covering at least one among the first and second semiconductor fins with a mask. The methods may further include depositing a compound semiconductor layer including the first and second semiconductor materials directly onto sidewalls of the first and second semiconductor fins not covered by the mask and oxidizing the compound semiconductor layer. The oxidization process oxidizes the first semiconductor material within the compound semiconductor layer while driving the second semiconductor material within the compound semiconductor layer into the sidewalls of the first and second semiconductor fins not covered by the mask.

    Abstract translation: 提供了制造具有不同阈值电压的鳍式晶体管的集成电路器件的方法。 所述方法可以包括分别形成包括第一和第二半导体材料的第一和第二半导体鳍片，并用掩模覆盖第一和第二半导体鳍片中的至少一个。 所述方法还可以包括将包括第一和第二半导体材料的化合物半导体层直接沉积在未被掩模覆盖的第一和第二半导体鳍片的侧壁上，并氧化化合物半导体层。 氧化过程将化合物半导体层内的第一半导体材料氧化，同时将化合物半导体层内的第二半导体材料驱动到未被掩模覆盖的第一和第二半导体鳍片的侧壁中。

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