公开(公告)号：US09805795B2

公开(公告)日：2017-10-31

申请号：US15265825

申请日：2016-09-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Titash Rakshit ,  Borna Obradovic

IPC: G11C11/00 ,  G11C14/00 ,  G11C11/18 ,  G11C11/16 ,  H01L43/08 ,  H01L43/04 ,  H01L43/06 ,  H01L43/10

CPC classification number: G11C14/0081 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/18 ,  G11C14/00 ,  H01L43/04 ,  H01L43/06 ,  H01L43/08 ,  H01L43/10

Abstract: A non-volatile data retention circuit, which is configured to store complementary volatile charge states of an external latch, comprises a coupled giant spin hall latch configured to generate and store complementary non-volatile spin states corresponding to the complementary volatile charge states of the external latch in response to receiving a charge current from the external latch, and to generate a differential charge current signal corresponding to the complementary non-volatile spin states in response to application of a read voltage, a write switch coupled to the coupled giant spin hall latch and configured to selectively enable flow of the charge current from the external latch to the coupled giant spin hall latch in response to a sleep signal, and a read switch coupled to the coupled giant spin hall latch and to selectively enable the application of the read voltage to the coupled giant spin hall latch.

公开(公告)号：US20170301672A1

公开(公告)日：2017-10-19

申请号：US15276768

申请日：2016-09-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Titash Rakshit ,  Mark Rodder ,  Rwik Sengupta

IPC: H01L27/092 ,  H01L29/66 ,  H01L29/423 ,  H01L29/167 ,  H01L29/08 ,  H01L23/528 ,  H01L23/522 ,  H01L21/8238

Abstract: An integrated circuit (IC) including a circuit block including a plurality of complementary metal oxide semiconductor field-effect transistors (CMOSFETs), and a tunnel field-effect transistor (TFET) between the circuit block and ground for power gating the circuit block.

公开(公告)号：US09773904B2

公开(公告)日：2017-09-26

申请号：US15132960

申请日：2016-04-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Borna Obradovic ,  Chris Bowen ,  Titash Rakshit ,  Palle Dharmendar ,  Mark Rodder

IPC: H01L29/78 ,  H01L29/786 ,  H01L29/423 ,  H01L29/66 ,  H01L21/8234

CPC classification number: H01L29/7842 ,  H01L21/28247 ,  H01L21/823487 ,  H01L29/42392 ,  H01L29/66522 ,  H01L29/66666 ,  H01L29/66742 ,  H01L29/7827 ,  H01L29/78642 ,  H01L29/78681 ,  H01L29/78696

Abstract: A vertical field effect device includes a substrate and a vertical channel including InxGa1-xAs on the substrate. The vertical channel includes a pillar that extends from the substrate and includes opposing vertical surfaces. The device further includes a stressor layer on the opposing vertical surfaces of the vertical channel. The stressor layer includes a layer of epitaxial crystalline material that is epitaxially formed on the vertical channel and that has lattice constant in a vertical plane corresponding to one of the opposing vertical surfaces of the vertical channel that is greater than a corresponding lattice constant of the vertical channel.

公开(公告)号：US11983622B2

公开(公告)日：2024-05-14

申请号：US18111471

申请日：2023-02-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Borna J. Obradovic ,  Titash Rakshit ,  Mark S. Rodder

IPC: G06N3/065 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/788 ,  H01L29/808 ,  H10B41/30

CPC classification number: G06N3/065 ,  H01L29/40114 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7881 ,  H01L29/8083 ,  H10B41/30

Abstract: A neuromorphic device for the analog computation of a linear combination of input signals, for use, for example, in an artificial neuron. The neuromorphic device provides non-volatile programming of the weights, and fast evaluation and programming, and is suitable for fabrication at high density as part of a plurality of neuromorphic devices. The neuromorphic device is implemented as a vertical stack of flash-like cells with a common control gate contact and individually contacted source-drain (SD) regions. The vertical stacking of the cells enables efficient use of layout resources.

公开(公告)号：US20210124984A1

公开(公告)日：2021-04-29

申请号：US16839043

申请日：2020-04-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Titash Rakshit ,  Malik Aqeel Anwar ,  Ryan Hatcher

IPC: G06K9/62 ,  G06N3/04 ,  G06N3/08 ,  G06F17/16 ,  G06K9/46

Abstract: A method of pipelining inference of a neural network, which includes an i-th layer (i being an integer greater than zero) and an (i+1)-th layer, includes processing, for a first input image, first i-th values of the i-th layer to generate first (i+1)-th values for the (i+1)-th layer, processing, for the first input image, the first (i+1)-th values of the (i+1)-th layer to generate output values, and concurrently with processing, for the first image, the (i+1)-th values, processing, for a second input image, second i-th values of the i-th layer to generate second (i+1)-th values.

公开(公告)号：US20200279605A1

公开(公告)日：2020-09-03

申请号：US16448820

申请日：2019-06-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ryan M. Hatcher ,  Titash Rakshit ,  Jorge Kittl ,  Rwik Sengupta ,  Dharmendar Palle ,  Joon Goo Hong

IPC: G11C13/00 ,  G11C11/22 ,  G11C11/16

Abstract: A weight cell and device are herein disclosed. The weight cell includes a first field effect transistor (FET) and a first resistive memory element connected to a drain of the first FET, a second FET and a second resistive memory element connected to a drain of the second FET, the drain of the first FET is connected to a gate of the second FET and the drain of the second FET is connected to a gate of the first FET, and a third FET, and a load resistor connected to a drain of the third FET.

公开(公告)号：US20200265892A1

公开(公告)日：2020-08-20

申请号：US16448799

申请日：2019-06-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ryan M. HATCHER ,  Titash Rakshit ,  Jorge Kittl ,  Rwik Sengupta ,  Dharmendar Palle ,  Joon Goo Hong

IPC: G11C13/00 ,  G11C11/22 ,  G11C11/16

Abstract: A weight cell and device are herein disclosed. The weight cell includes a first field effect transistor (FET) and a first resistive memory element connected to a drain of the first FET, and a second FET and a second resistive memory element connected to a drain of the second FET. The drain of the first FET is connected to a gate of the second FET and the drain of the second FET is connected to a gate of the first FET.

公开(公告)号：US10739186B2

公开(公告)日：2020-08-11

申请号：US15886753

申请日：2018-02-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ryan M. Hatcher ,  Jorge A. Kittl ,  Borna J. Obradovic ,  Titash Rakshit

IPC: G11C7/10 ,  G11C13/00 ,  G01G23/38 ,  G06G7/16 ,  G11C11/54 ,  G06N3/063 ,  G11C11/16

Abstract: A weight cell including first and second bi-directional memory elements each configured to switch between a first resistance state and a second resistance state different than the first resistance state. A first input line is connected to a first terminal of the first bi-directional memory element, and a second input line is connected to the first terminal of the second bi-directional memory element. A first diode in forward bias connects the second terminal of the first bi-directional memory element to a first output line, a second diode in reverse bias connects the second terminal of the second bi-directional memory element to a second output line, a third diode in reverse bias connects the second terminal of the first bi-directional memory element to the second output line, and a fourth diode in forward bias connects the second terminal of the second bi-directional memory element to the first output line.

公开(公告)号：US20190319108A1

公开(公告)日：2019-10-17

申请号：US16141767

申请日：2018-09-25

Applicant: Samsung Electronics Co., LTD.

Inventor： Jorge A. Kittl ,  Borna J. Obradovic ,  Ryan M. Hatcher ,  Titash Rakshit

IPC: H01L29/51 ,  H01L27/088 ,  H01L29/66

Abstract: A semiconductor device and method for providing a semiconductor device are described. The semiconductor device includes a channel, a gate, and a multilayer gate insulator structure between the gate and the channel. The multilayer gate insulator structure includes at least one ferroelectric layer and at least one dielectric layer. The at least one ferroelectric layer and the at least one dielectric layer share at least one interface and have a strong polarization coupling.

公开(公告)号：US20190318774A1

公开(公告)日：2019-10-17

申请号：US16142944

申请日：2018-09-26

Applicant: Samsung Electronics Co., LTD.

Inventor： Jorge A. Kittl ,  Borna J. Obradovic ,  Ryan M. Hatcher ,  Titash Rakshit

IPC: G11C11/22

Abstract: A semiconductor memory device and method for providing the semiconductor memory device are described. The semiconductor memory device includes a ferroelectric capacitor. The ferroelectric capacitor includes a first electrode, a second electrode and a multilayer insulator structure between the first and second electrodes. The multilayer insulator structure includes at least one ferroelectric layer and at least one dielectric layer. The at least one ferroelectric layer and the at least one dielectric layer share at least one interface and have a strong polarization coupling.