公开(公告)号：US20230307062A1

公开(公告)日：2023-09-28

申请号：US18326606

申请日：2023-05-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Soyeong GWAK ,  Raeyoung LEE ,  Jinkyu KANG ,  Sejun PARK ,  Changhwan SHIN ,  Jaeduk LEE ,  Woojae JANG

IPC: G11C16/16 ,  G11C16/26 ,  G11C16/34 ,  G11C7/10 ,  G11C16/24 ,  G11C16/08

CPC classification number: G11C16/16 ,  G11C16/26 ,  G11C16/349 ,  G11C7/1087 ,  G11C16/24 ,  G11C7/106 ,  G11C16/08

Abstract: An operating method of a storage device includes reading a wear-out pattern of a memory block when a controller determines the memory block is a re-use memory block of a non-volatile memory device; selecting an operation mode corresponding to the read wear-out pattern using the controller; and transmitting the selected operation mode to the non-volatile memory device using the controller.

公开(公告)号：US20240395649A1

公开(公告)日：2024-11-28

申请号：US18640201

申请日：2024-04-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chulmin CHOI ,  Nambin KIM ,  Samki KIM ,  Taehun KIM ,  Seungjae BAIK ,  Jaeduk LEE

IPC: H01L23/31 ,  H01L23/29 ,  H01L23/522 ,  H10B12/00

Abstract: Provided is a semiconductor device including a semiconductor substrate, a gate stack including a plurality of gate layers and a plurality of insulation layers alternately stacked on the semiconductor substrate, a plurality of first channel structures penetrating through the gate stack and extending in a vertical direction, a word line cut penetrating through the gate stack and extending in the vertical direction, a passivation layer disposed on the gate stack, and a string select line stack disposed on the passivation layer, wherein the passivation layer includes a first passivation layer containing a passivation element and a second passivation layer having a smaller content of the passivation element than the first passivation layer.

公开(公告)号：US20240297117A1

公开(公告)日：2024-09-05

申请号：US18519551

申请日：2023-11-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunjung KIM ,  Sejun PARK ,  Jaeduk LEE ,  Eiwhan JUNG

IPC: H01L23/528 ,  H01L23/522 ,  H01L25/065 ,  H01L29/423 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B80/00

CPC classification number: H01L23/5283 ,  H01L23/5226 ,  H01L25/0652 ,  H01L29/42328 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B80/00 ,  H01L2225/06506

Abstract: A semiconductor device includes a first semiconductor structure including a substrate, circuit devices on the substrate, and circuit interconnection lines on the circuit devices; and a second semiconductor structure on the first semiconductor structure and having a first region and a second region, wherein the second semiconductor structure includes gate electrodes; first channel structures in the first region; second channel structures in the first region; and contact plugs in the second region, the gate electrodes include first gate electrodes having a first thickness in the vertical direction in the first region and second gate electrodes having a second thickness in the vertical direction greater than the first thickness in the first region, and the second gate electrodes are commonly connected to one of the contact plugs.

公开(公告)号：US20240130133A1

公开(公告)日：2024-04-18

申请号：US18446911

申请日：2023-08-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sohyeon LEE ,  Seongpil CHANG ,  Sea Hoon LEE ,  Jaeduk LEE ,  Tackhwi LEE

IPC: H10B43/40 ,  H01L23/528 ,  H10B41/27 ,  H10B41/40 ,  H10B43/27

CPC classification number: H10B43/40 ,  H01L23/5283 ,  H10B41/27 ,  H10B41/40 ,  H10B43/27

Abstract: A vertical nonvolatile memory device may include a peripheral circuit portion including a memory cell driving circuit and connection wiring; a first hydrogen diffusion barrier layer above the peripheral circuit portion; a first insulating layer above the first hydrogen diffusion barrier layer; a common source line layer above the first insulating layer; a second hydrogen diffusion barrier layer above the first insulating layer; and a memory cell stack structure above the common source line layer and the second hydrogen diffusion barrier layer.

公开(公告)号：US20200350326A1

公开(公告)日：2020-11-05

申请号：US16668222

申请日：2019-10-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Janggn YUN ,  Jaeduk LEE

IPC: H01L27/11548 ,  H01L27/11556 ,  H01L27/11582 ,  H01L23/522 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11575

Abstract: A semiconductor device includes a substrate including a memory cell region and a connection region, a plurality of gate electrodes stacked on the substrate, a channel structure penetrating the plurality of gate electrodes and including a channel layer extending in a vertical direction perpendicular to an upper surface of the substrate in the memory cell region, a dummy channel structure penetrating the plurality of gate electrodes and including a dummy channel layer extending in the vertical direction in the connection region, a first semiconductor layer disposed between the substrate and a lowermost one of the plurality of gate electrodes and surrounding the channel structure in the memory cell region, and an insulating separation structure disposed between the substrate and the lowermost one of the plurality of gate electrodes and surrounding the dummy channel layer.

公开(公告)号：US20200161179A1

公开(公告)日：2020-05-21

申请号：US16751744

申请日：2020-01-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dohyun LEE ,  Youngwoo PARK ,  Junghoon PARK ,  Jaeduk LEE

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11573

Abstract: A semiconductor device includes a semiconductor pattern on a semiconductor substrate, a three-dimensional memory array on the semiconductor pattern, and a peripheral interconnection structure between the semiconductor pattern and the semiconductor substrate. The peripheral interconnection structure includes an upper interconnection structure on a lower interconnection structure. The upper interconnection structure includes an upper interconnection and an upper barrier layer. The lower interconnection structure includes a lower interconnection and a lower barrier layer. The upper barrier layer is under a bottom surface of the upper interconnection and does not cover side surfaces of the upper interconnection. The lower barrier layer is under a bottom surface of the lower interconnection and covers side surfaces of the lower interconnection.

公开(公告)号：US20180294274A1

公开(公告)日：2018-10-11

申请号：US15696276

申请日：2017-09-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sohyeon LEE ,  Sunil SHIM ,  Jaeduk LEE ,  Jaehoon JANG ,  Jeehoon HAN

IPC: H01L27/11565 ,  H01L27/1157 ,  H01L27/11582 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768

CPC classification number: H01L27/11565 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/1157 ,  H01L27/11582

Abstract: A three-dimensional semiconductor device and a method of manufacturing the same are provided. The three-dimensional semiconductor device includes a stack structure including insulating layers and electrodes that are alternately stacked on a substrate, a horizontal semiconductor pattern between the substrate and the stack structure, vertical semiconductor patterns penetrating the stack structure and connected to the horizontal semiconductor pattern; and a common source plug at a side of the stack structure. The stack structure, the horizontal semiconductor pattern and the common source plug extend in a first direction. The horizontal semiconductor pattern includes a first sidewall extending in the first direction. The first sidewall has protrusions protruding toward the common source plug.

公开(公告)号：US20250078929A1

公开(公告)日：2025-03-06

申请号：US18679809

申请日：2024-05-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kibong MOON ,  Suck-Soo KIM ,  Tae Hun KIM ,  Hyoje BANG ,  Seung Jae BAIK ,  Sung-Bok LEE ,  Jaeduk LEE ,  Junhee LIM

IPC: G11C16/04 ,  G11C5/06 ,  H01L25/065 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40 ,  H10B80/00

Abstract: A semiconductor device may include a substrate, a plurality of cell strings perpendicular to an upper surface of the substrate, and a bit line connected to at least six of the cell strings. Each of the cell strings may include a plurality of memory cells connected in series to each other in a direction perpendicular to the upper surface of the substrate, first to fourth ground selection transistors connected in series to each other between the plurality of memory cells and the substrate, and a string selection transistor between the plurality of memory cells and the bit line. A first one of the first to fourth selection ground selection transistors may have a first threshold voltage distribution, and a second one of the first to fourth ground selection transistors may have a second threshold voltage distribution. The second threshold voltage distribution may be different from the first threshold voltage distribution.

公开(公告)号：US20230170295A1

公开(公告)日：2023-06-01

申请号：US17868899

申请日：2022-07-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joonam KIM ,  Sejun PARK ,  Jaeduk LEE ,  Gaeun KIM

IPC: H01L23/522 ,  H01L23/528 ,  H01L27/11556 ,  H01L27/11582

CPC classification number: H01L23/5226 ,  H01L23/528 ,  H01L27/11556 ,  H01L27/11582

Abstract: A semiconductor device may include a plurality of gate electrodes apart from each other in a vertical direction on a substrate; a plurality of channel structures penetrating the plurality of gate electrodes and extending in the vertical direction; and a plurality of bit lines arranged on and connected to the plurality of channel structures. The plurality of bit lines may include a plurality of lower bit lines and a plurality of upper bit lines at different vertical levels from each other to constitute at least two layers. The plurality of upper bit lines may be apart from each other in a first horizontal direction and extend in parallel with each other in a second horizontal direction perpendicular to the first horizontal direction. A lower expansion space may be defined between two lower bit lines adjacent to each other among the plurality of lower bit lines.

公开(公告)号：US20230071420A1

公开(公告)日：2023-03-09

申请号：US17874927

申请日：2022-07-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tae In LEE ,  Byung Jin CHO ,  Jung Hoon LEE ,  Jaeduk LEE

IPC: H01L27/11582 ,  H01L27/11573

Abstract: A three-dimensional semiconductor memory device may include a substrate, a stack structure including interlayer dielectric layers and gate electrodes alternately and repeatedly stacked on the substrate, and vertical channel structures provided in vertical channel holes penetrating the stack structure. Each of the vertical channel structures may include a data storage pattern covering an inner side surface of each of the vertical channel holes, a vertical semiconductor pattern covering the data storage pattern, and a gapfill insulating pattern filling an internal space enclosed by the vertical semiconductor pattern. The vertical semiconductor pattern may have a first surface which is in contact with the gapfill insulating pattern, and a second surface which is in contact with the data storage pattern. A germanium concentration in the vertical semiconductor pattern may decrease in a direction from the first surface toward the second surface.