公开(公告)号：US20240395649A1

公开(公告)日：2024-11-28

申请号：US18640201

申请日：2024-04-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chulmin CHOI ,  Nambin KIM ,  Samki KIM ,  Taehun KIM ,  Seungjae BAIK ,  Jaeduk LEE

IPC: H01L23/31 ,  H01L23/29 ,  H01L23/522 ,  H10B12/00

Abstract: Provided is a semiconductor device including a semiconductor substrate, a gate stack including a plurality of gate layers and a plurality of insulation layers alternately stacked on the semiconductor substrate, a plurality of first channel structures penetrating through the gate stack and extending in a vertical direction, a word line cut penetrating through the gate stack and extending in the vertical direction, a passivation layer disposed on the gate stack, and a string select line stack disposed on the passivation layer, wherein the passivation layer includes a first passivation layer containing a passivation element and a second passivation layer having a smaller content of the passivation element than the first passivation layer.

公开(公告)号：US20250126792A1

公开(公告)日：2025-04-17

申请号：US18990188

申请日：2024-12-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Suhwan LIM ,  Nambin KIM ,  Samki KIM ,  Taehun KIM ,  Hanvit YANG ,  Changhee LEE ,  Jaehun JUNG ,  Hyeongwon CHOI

IPC: H10B43/27 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/35 ,  H10B43/40

Abstract: A semiconductor device includes a lower structure including a semiconductor substrate and circuit devices on the semiconductor substrate; a stack structure including interlayer insulating layers and gate electrodes alternating in a vertical direction; and a channel structure penetrating the stack structure. The channel structure includes a core insulating layer, a channel layer, a gate dielectric layer, and a channel pad. A portion of the channel pad overlaps an uppermost gate electrode among the gate electrodes in a horizontal direction. The channel pad includes a first pad layer and a second pad layer on the first pad layer. The second pad layer includes doped polysilicon that is doped with impurities and having N-type conductivity. The first pad layer includes at least one of an undoped polysilicon region and a doped polysilicon region having N-type conductivity and having an impurity concentration lower than an impurity concentration of the second pad layer.

公开(公告)号：US20240389322A1

公开(公告)日：2024-11-21

申请号：US18621916

申请日：2024-03-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Samki KIM ,  Nambin KIM ,  Taehun KIM

IPC: H10B41/35 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: A non-volatile memory device may include a substrate having a cell region and a connection region, an electrode structure including electrodes stacked on the substrate and an insulating pattern covering an uppermost electrode among the electrodes, a vertical structure connected with the substrate through the electrode structure in the cell region, a filling insulating layer covering the electrode structure in the connection region, a buffer insulating layer on a cover insulating layer, a conductive pattern, and an upper semiconductor pattern connected with the conductive pattern through the buffer insulating layer. The cover insulating layer may cover the electrode structure, the vertical structure, and the filling insulating layer, and may include a through hole in the cell region and at least one through opening in the connection region. The conductive pattern may have at least a portion in the through hole, and may be connected with the vertical structure.

公开(公告)号：US20240121958A1

公开(公告)日：2024-04-11

申请号：US18243200

申请日：2023-09-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Samki KIM ,  Nambin KIM ,  Taehun KIM ,  Suhwan LIM ,  Hyeongwon CHOI

IPC: H10B43/27

CPC classification number: H10B43/27

Abstract: A vertical semiconductor device includes; a pattern structure including a plurality of insulation patterns and a plurality of gate electrodes that are alternately and repeatedly stacked on a substrate, wherein the pattern structure includes a first gate electrode serving as a gate electrode of an erase transistor, wherein the first gate electrode is one of the plurality of gate electrodes; and a channel structure in a channel hole passing through the pattern structure, wherein the channel structure includes a data storage structure, a first channel, an undoped semiconductor liner, a doped semiconductor pattern, a filling insulation pattern and a capping pattern, wherein the data storage structure, the first channel, the undoped semiconductor liner, and the doped semiconductor pattern are sequentially disposed on a sidewall of the first gate electrode.

公开(公告)号：US20230035421A1

公开(公告)日：2023-02-02

申请号：US17720376

申请日：2022-04-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Suhwan LIM ,  Nambin KIM ,  Samki KIM ,  Taehun KIM ,  Hanvit YANG ,  Changhee LEE ,  Jaehun JUNG ,  Hyeongwon CHOI

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11526

Abstract: A semiconductor device includes a lower structure including a semiconductor substrate and circuit devices on the semiconductor substrate; a stack structure including interlayer insulating layers and gate electrodes alternating in a vertical direction; and a channel structure penetrating the stack structure. The channel structure includes a core insulating layer, a channel layer, a gate dielectric layer, and a channel pad. A portion of the channel pad overlaps an uppermost gate electrode among the gate electrodes in a horizontal direction. The channel pad includes a first pad layer and a second pad layer on the first pad layer. The second pad layer includes doped polysilicon that is doped with impurities and having N-type conductivity. The first pad layer includes at least one of an undoped polysilicon region and a doped polysilicon region having N-type conductivity and having an impurity concentration lower than an impurity concentration of the second pad layer.