公开(公告)号：US20230165002A1

公开(公告)日：2023-05-25

申请号：US18053484

申请日：2022-11-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Suhwan LIM ,  Sanghoon KIM ,  Chungje NA

IPC: H01L29/76

CPC classification number: H01L27/11582 ,  H01L27/11519 ,  H01L27/1157 ,  H01L27/11556 ,  H01L27/11526 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/11573

Abstract: A semiconductor device includes a lower structure; a pattern structure including first to third pattern layers sequentially stacked on the lower structure; gate electrodes stacked on the pattern structure and spaced apart from each other in a first direction that is perpendicular to an upper surface of the pattern structure, and a channel structure passing through the gate electrodes. The channel structure includes a channel layer and a metal-semiconductor compound layer. The metal-semiconductor compound layer contacts the channel layer and the second pattern layer. The channel structure passes through the second and third pattern layers and extends into the first pattern layer. The second pattern layer has a first metal layer contacting the metal-semiconductor compound layer. At least a portion of the metal-semiconductor compound layer overlaps the lower gate electrode in a second direction perpendicular to the first direction.

公开(公告)号：US20240170072A1

公开(公告)日：2024-05-23

申请号：US18510074

申请日：2023-11-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Suhwan LIM ,  Kyunghwan LEE ,  Yongseok KIM

IPC: G11C16/16 ,  G11C16/04 ,  G11C16/24 ,  G11C16/32

CPC classification number: G11C16/16 ,  G11C16/0433 ,  G11C16/24 ,  G11C16/32

Abstract: A storage device capable of performing erase operations in units smaller than blocks may include nonvolatile memory, and processing circuitry configured to, apply an erase voltage to a first bit line of the plurality of bit lines of at least one memory block of the plurality of memory blocks, apply an erase prohibition voltage to a second bit line of the plurality of bit lines, the erase prohibition voltage having a voltage level lower than a voltage level of the erase voltage, and float the common source line to cause an erasure of data stored in at least one first memory cell included in at least one first cell string connected to the first bit line by floating the common source line, and preserve data stored in at least one second memory cell included in at least one second cell string connected to the second bit line.

公开(公告)号：US20240023340A1

公开(公告)日：2024-01-18

申请号：US18222278

申请日：2023-07-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Suhwan LIM ,  Yongseok Kim ,  Juhyung Kim ,  Minjun Lee

IPC: H10B51/30 ,  H10B51/10 ,  H10B51/40 ,  H10B80/00 ,  H01L25/065 ,  H10B43/10 ,  H10B43/27 ,  H10B43/40 ,  H10B43/35 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40

CPC classification number: H10B51/30 ,  H10B51/10 ,  H10B51/40 ,  H10B80/00 ,  H01L25/0652 ,  H10B43/10 ,  H10B43/27 ,  H10B43/40 ,  H10B43/35 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H01L2225/06506

Abstract: The present disclosure provides methods, apparatuses, and systems for operating and manufacturing a semiconductor device. In some embodiments, a semiconductor device includes a stack structure including interlayer insulating layers and gate electrodes, a channel layer disposed inside a hole penetrating through the stack structure, a data storage layer disposed between the stack structure and the channel layer, data storage patterns disposed between the data storage layer and the gate electrodes, and dielectric layers disposed between the data storage patterns and the gate electrodes. The interlayer insulating layers and the gate electrodes are alternately and repeatedly stacked in a first direction. A first material of the data storage layer is different from a second material of the data storage patterns.

公开(公告)号：US20220005826A1

公开(公告)日：2022-01-06

申请号：US17148334

申请日：2021-01-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Suhwan LIM ,  Jaehun JUNG ,  Sanghoon KIM ,  Taehun KIM ,  Seongchan LEE

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11565 ,  H01L27/11573

Abstract: A semiconductor device includes gate electrodes and insulating layers spaced apart from each other on a substrate and alternately stacked in a direction perpendicular to an upper surface of the substrate, and channel structures that extend through stack structures. Ones of the structures include a channel insulating layer, a pad layer on the channel insulating layer, and a channel layer. The channel layer includes a first channel region, and a second channel region including a semiconductor material having a length shorter than a length of the first channel region and having an impurity concentration of a first conductivity type and the pad layer includes a semiconductor material doped with a second conductivity type impurity. A height level of a lower surface of the second channel region is lower than a height level of a lower surface of a first erase gate electrode.

公开(公告)号：US20250024684A1

公开(公告)日：2025-01-16

申请号：US18672512

申请日：2024-05-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sanghyun PARK ,  Hyuncheol KIM ,  Suhwan LIM ,  Siyeon CHO

IPC: H10B51/20 ,  H10B51/30

Abstract: A vertical semiconductor device includes a substrate, a stacked structure including a plurality of insulation patterns and a plurality of gate electrode structures alternately and repeatedly stacked on the substrate in a vertical direction substantially perpendicular to a surface of the substrate, a channel pattern passing through the stacked structure, a gate insulation layer surrounding an outer wall of the channel pattern, and a gate insulation pattern disposed between the gate insulation layer and the gate electrode structures. The gate insulation layer includes a metal oxide having paraelectricity, and the gate insulation pattern has ferroelectricity. The gate insulation layer includes a first portion contacting one of the insulation patterns and a second portion contacting the gate insulation pattern.

公开(公告)号：US20250151280A1

公开(公告)日：2025-05-08

申请号：US18918694

申请日：2024-10-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Suseong NOH ,  Kwangsoo KIM ,  Taeyoung KIM ,  Ilho MYEONG ,  Sanghyun PARK ,  Suhwan LIM

IPC: H10B43/40 ,  G11C16/04 ,  H01L25/065 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B80/00

Abstract: A semiconductor device including a peripheral circuit structure, a cell structure including gate electrodes and stacked on the peripheral circuit structure, the cell structure including a cell region, a connection region, and a peripheral circuit connection region, the cell structure, a plurality of channel structures extending in a vertical direction through the gate electrodes in the cell region, each of the plurality of channel structures including a first end portion close to the peripheral circuit structure and a second end portion opposite to the first end portion, and a common source layer connected to the second end portion of each of the channel structures in the cell region may be provided.

公开(公告)号：US20250126792A1

公开(公告)日：2025-04-17

申请号：US18990188

申请日：2024-12-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Suhwan LIM ,  Nambin KIM ,  Samki KIM ,  Taehun KIM ,  Hanvit YANG ,  Changhee LEE ,  Jaehun JUNG ,  Hyeongwon CHOI

IPC: H10B43/27 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/35 ,  H10B43/40

Abstract: A semiconductor device includes a lower structure including a semiconductor substrate and circuit devices on the semiconductor substrate; a stack structure including interlayer insulating layers and gate electrodes alternating in a vertical direction; and a channel structure penetrating the stack structure. The channel structure includes a core insulating layer, a channel layer, a gate dielectric layer, and a channel pad. A portion of the channel pad overlaps an uppermost gate electrode among the gate electrodes in a horizontal direction. The channel pad includes a first pad layer and a second pad layer on the first pad layer. The second pad layer includes doped polysilicon that is doped with impurities and having N-type conductivity. The first pad layer includes at least one of an undoped polysilicon region and a doped polysilicon region having N-type conductivity and having an impurity concentration lower than an impurity concentration of the second pad layer.

公开(公告)号：US20240121958A1

公开(公告)日：2024-04-11

申请号：US18243200

申请日：2023-09-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Samki KIM ,  Nambin KIM ,  Taehun KIM ,  Suhwan LIM ,  Hyeongwon CHOI

IPC: H10B43/27

CPC classification number: H10B43/27

Abstract: A vertical semiconductor device includes; a pattern structure including a plurality of insulation patterns and a plurality of gate electrodes that are alternately and repeatedly stacked on a substrate, wherein the pattern structure includes a first gate electrode serving as a gate electrode of an erase transistor, wherein the first gate electrode is one of the plurality of gate electrodes; and a channel structure in a channel hole passing through the pattern structure, wherein the channel structure includes a data storage structure, a first channel, an undoped semiconductor liner, a doped semiconductor pattern, a filling insulation pattern and a capping pattern, wherein the data storage structure, the first channel, the undoped semiconductor liner, and the doped semiconductor pattern are sequentially disposed on a sidewall of the first gate electrode.

公开(公告)号：US20230035421A1

公开(公告)日：2023-02-02

申请号：US17720376

申请日：2022-04-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Suhwan LIM ,  Nambin KIM ,  Samki KIM ,  Taehun KIM ,  Hanvit YANG ,  Changhee LEE ,  Jaehun JUNG ,  Hyeongwon CHOI

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11526

Abstract: A semiconductor device includes a lower structure including a semiconductor substrate and circuit devices on the semiconductor substrate; a stack structure including interlayer insulating layers and gate electrodes alternating in a vertical direction; and a channel structure penetrating the stack structure. The channel structure includes a core insulating layer, a channel layer, a gate dielectric layer, and a channel pad. A portion of the channel pad overlaps an uppermost gate electrode among the gate electrodes in a horizontal direction. The channel pad includes a first pad layer and a second pad layer on the first pad layer. The second pad layer includes doped polysilicon that is doped with impurities and having N-type conductivity. The first pad layer includes at least one of an undoped polysilicon region and a doped polysilicon region having N-type conductivity and having an impurity concentration lower than an impurity concentration of the second pad layer.

公开(公告)号：US20210398998A1

公开(公告)日：2021-12-23

申请号：US17205563

申请日：2021-03-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaehun JUNG ,  Suhwan LIM ,  Hyeyoung KWON

IPC: H01L27/11556 ,  H01L27/11582 ,  G11C5/06 ,  H01L23/538

Abstract: A semiconductor device includes a substrate, a stack structure including interlayer insulating layers and gate electrodes alternately and repeatedly stacked on the substrate in a first direction perpendicular, a channel structure that penetrates the stack structure, a contact plug disposed on the channel structure, and a bit line on the contact plug. The channel structure includes a core pattern, a pad structure on the core pattern, and a channel layer on a side surface of the core pattern and a side surface of the pad structure. The pad structure includes a pad pattern, a first pad layer, and a second pad layer, the first pad layer that is between the channel layer and the pad pattern, and the second pad layer including a first portion between the channel layer and the first pad layer, and a second portion between the first pad layer and the core pattern.