公开(公告)号：US20250040154A1

公开(公告)日：2025-01-30

申请号：US18624857

申请日：2024-04-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hakseon KIM ,  Dongjin LEE ,  Jaeduk LEE ,  Kangoh YUN

IPC: H10B80/00 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27 ,  H10B43/40

Abstract: A semiconductor device includes a peripheral circuit structure; and a cell structure on the peripheral circuit structure, wherein the peripheral circuit structure comprises: a substrate comprising a cell region, a connection region adjacent to the cell region, and a pad region extending around the cell region and the connection region; a first connection structure between the substrate and the cell structure; a first peripheral circuit transistor in the cell region and/or the connection region; and a second peripheral circuit transistor in the pad region, wherein the first connection structure includes a first wiring structure and a dummy structure, the first wiring structure is electrically connected to the first peripheral circuit transistor and/or the second peripheral circuit transistor, and the dummy structure is not directly connected to the first peripheral circuit transistor.

公开(公告)号：US20240282377A1

公开(公告)日：2024-08-22

申请号：US18441331

申请日：2024-02-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chaehyeon LIM ,  Woojae JANG ,  Sejun PARK ,  Yujeong SEO ,  Jaeduk LEE

IPC: G11C16/08 ,  G11C16/04 ,  G11C16/32

CPC classification number: G11C16/08 ,  G11C16/0433 ,  G11C16/32

Abstract: Provided is an operating method of a nonvolatile memory device including a plurality of cell strings, each cell string of the plurality of cell strings including a plurality of memory cells, connected between a bit line and a common source line, and vertical holes penetrating a plurality of word lines stacked in a direction perpendicular to a substrate, the operating method including applying a word line voltage to the plurality of word lines, classifying the plurality of word lines into a plurality of regions, each region of the plurality of regions including at least one of the word lines, and recovering voltages of the plurality of word lines by recovering voltages of word lines arranged in a central region among the plurality of regions before recovering voltages of word lines in other regions of the plurality of regions.

公开(公告)号：US20230042249A1

公开(公告)日：2023-02-09

申请号：US17722850

申请日：2022-04-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Guyeon HAN ,  Sangwon PARK ,  Jinkyu KANG ,  Raeyoung LEE ,  Jaeduk LEE

IPC: G06F3/06

Abstract: Provided are a memory device storing setting data and a memory system including the same. The memory device may include a cell array including a plurality of cell blocks, each including a plurality of pages, and a control logic that controls a program and read operation on the cell array, wherein at least one page of the cell array stores information data read (IDR) data including information related to a setting operation of the memory device, at least one other page of the cell array stores replica IDR data including inverted bit values of the IDR data, and the control logic controls a recovery operation for repairing errors in the IDR data by reading the replica IDR data when a read fail of the IDR data occurs.

公开(公告)号：US20230019217A1

公开(公告)日：2023-01-19

申请号：US17709790

申请日：2022-03-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tackhwi LEE ,  Jaeduk LEE ,  Hojun LEE ,  Seongpil CHANG

IPC: H01L27/112 ,  G11C16/08 ,  G11C16/12

Abstract: A non-volatile memory device comprises a memory cell region including a plurality of cell transistors, a first-type semiconductor substrate including a peripheral circuit region including circuits configured to control the plurality of cell transistors, and a plurality of pass transistors on the peripheral circuit region of the semiconductor substrate, wherein the peripheral circuit region includes a first region and a second region which are doped to a depth at an upper portion of the semiconductor substrate while being insulated from each other by an implant region, wherein the first region is a second type different from the first type, and includes a first doped region, and a first well region beneath the first doped region and configured to have a higher doping concentration than the first doped region, wherein the second region is the first type, and includes a second doped region, and a second well region beneath the second doped region and configured to have a higher doping concentration than the second doped region, wherein a first pass transistor on the first region from among the plurality of pass transistors is connected to a string selection line or a ground selection transistor, wherein a second pass transistor on the second region from among the plurality of pass transistors is connected to a word line, wherein a positive voltage or a negative voltage is configured to be applied to the second well region during operation of the second pass transistor.

公开(公告)号：US20210143172A1

公开(公告)日：2021-05-13

申请号：US17036034

申请日：2020-09-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Janggn YUN ,  Jaeduk LEE ,  Dongwhee KWON

IPC: H01L27/11582 ,  H01L27/24 ,  H01L27/11556 ,  H01L23/535

Abstract: A semiconductor device includes a first stacked structure and a second stacked structure spaced apart from each other on a substrate, and a plurality of separation structures and a plurality of vertical memory structures alternately arranged between the first stacked structure and the second stacked structure in a first direction parallel to an upper surface of the substrate. Each of the first and second stacked structures includes a plurality of interlayer insulating layers and a plurality of gate layers alternately repeatedly stacked on the lower structure. Each of the vertical memory structures includes a first data storage structure facing the first stacked structure and a second data storage structure facing the second stacked structure. Side surfaces of the first and second stacked structures facing the vertical memory structures are concave in a plan view.

公开(公告)号：US20210043649A1

公开(公告)日：2021-02-11

申请号：US16936888

申请日：2020-07-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangyong PARK ,  Hyunseok NA ,  Jaeduk LEE

IPC: H01L27/11582 ,  H01L27/11556

Abstract: An integrated circuit device includes a plurality of conductive lines extending in a horizontal direction parallel to a main surface of a substrate and overlapping one another in a vertical direction vertical to the main surface, on the substrate, a plurality of insulation layers each between two adjacent conductive lines of the plurality of conductive lines to extend in the horizontal direction, a channel layer extending in the vertical direction in a channel hole passing through the plurality of conductive lines and the plurality of insulation layers, and a plurality of outer blocking dielectric layers between the plurality of conductive lines and the channel layer, in at least some of the plurality of conductive lines, wherein a width of each of the plurality of outer blocking dielectric layers in the horizontal direction increases toward the main surface.

公开(公告)号：US20250126799A1

公开(公告)日：2025-04-17

申请号：US18673528

申请日：2024-05-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kang-Oh YUN ,  Yunjo LEE ,  Dongjin LEE ,  Jaeduk LEE

IPC: H10B43/40 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27

Abstract: A semiconductor device may include a substrate containing first to third doping regions, first and second gate structures between the first and second doping regions, and a gate separation layer between the first and second gate structures. Each of the first and second gate structures may include a first gate dielectric layer, a first gate conductive layer on the first gate dielectric layer, and a second gate conductive layer between the gate separation layer and the first gate conductive layer. The gate separation layer may include a first sidewall in contact with the first gate structure and a second sidewall in contact with the second gate structure. A top surface of the gate separation layer may be at a same level as a top surface of the second gate conductive layer.

公开(公告)号：US20250014644A1

公开(公告)日：2025-01-09

申请号：US18893085

申请日：2024-09-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaeduk LEE ,  Kinam Kim ,  Sujin Ahn

IPC: G11C16/04 ,  H01L23/522 ,  H01L23/528 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

Abstract: Provided are semiconductor devices and data storage systems including the same. The semiconductor devices may include first and second separation structures parallel to each other, a block between the first and second separation structures, and bit lines on the block. The block includes strings, the bit lines include a first bit line electrically connected to first and second strings, each of the strings includes a lower select transistor, memory cell transistors, and upper select transistors connected in series, the upper select transistors in each of the strings include a first upper select transistor and a second upper select transistor below the first upper select transistor. The first upper select transistors of the first and second strings may share a single first upper select gate electrode. Gate electrodes of the lower select transistors of the first and second strings may include surfaces coplanar with each other.

公开(公告)号：US20250008726A1

公开(公告)日：2025-01-02

申请号：US18514801

申请日：2023-11-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kang Lib KIM ,  Jaeduk LEE ,  Sea Hoon LEE ,  Tackhwi LEE ,  Seongpil CHANG

IPC: H10B41/27 ,  H01L23/48 ,  H01L25/065 ,  H10B41/10 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B80/00

Abstract: A semiconductor device includes a first substrate; a wiring layer on the first substrate; a second substrate on the wiring layer and including a conductive material; a first horizontal conductive layer and a second horizontal conductive layer sequentially stacked on the second substrate and connected to the second substrate; a gate stacking structure including an interlayer insulating layer and a gate electrode alternately stacked on the second horizontal conductive layer; a channel structure passing through the gate stacking structure and connected to the second substrate; a first capacitor electrode on a same layer as the second substrate; a second capacitor electrode overlapping the first capacitor electrode; and a first dielectric layer between the first capacitor electrode and the second capacitor electrode, wherein the second capacitor electrode is on a same layer as at least one of the wiring layer, the second substrate, the first horizontal conductive layer, or the gate electrode.

公开(公告)号：US20240121952A1

公开(公告)日：2024-04-11

申请号：US18232568

申请日：2023-08-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sohyeon LEE ,  Seahoon LEE ,  Jaeduk LEE ,  Tackhwi LEE

IPC: H10B41/27 ,  H10B41/10 ,  H10B43/10 ,  H10B43/27

CPC classification number: H10B41/27 ,  H10B41/10 ,  H10B43/10 ,  H10B43/27

Abstract: A vertical memory device includes a substrate, first and second sub-semiconductor patterns, first and second common source contacts, and first and second cell structures. The substrate includes a first region and a second region having a same length as the first region in a first direction, the first region having a first width in a second direction perpendicular to the first direction, and the second region having a second width in the second direction that is less than the first width. The first sub-semiconductor pattern covers the first region, and a portion of the first sub-semiconductor pattern has a first thickness. The second sub-semiconductor pattern covers the second region and has a second thickness that is less than the first thickness. The first and second common source contacts are disposed on edges in the second direction of the first and second patterns, respectively.