公开(公告)号：US20250040140A1

公开(公告)日：2025-01-30

申请号：US18603505

申请日：2024-03-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju Seong MIN ,  Jun Gyeom KIM ,  Hyun Min KIM ,  Kang-Oh YUN ,  Taek Kyu YOON ,  Dong Jin LEE ,  Jae Duk LEE ,  Jee Hoon HAN

IPC: H10B43/40 ,  G11C5/06 ,  G11C16/04 ,  H01L25/065 ,  H10B43/27 ,  H10B43/35 ,  H10B80/00

Abstract: A semiconductor memory device comprises a cell structure and a peripheral circuit structure electrically connected to the cell structure. The peripheral circuit structure comprises an active region, a first gate structure comprising a first gate insulating layer intersecting the active region and in contact with the active region, a second gate structure comprising a second gate insulating layer spaced apart from the first gate structure, and in contact with the active region, and a source/drain region between the first gate structure and the second gate structure. A thickness of the first gate insulating layer is less than a thickness of the second gate insulating layer. The source/drain region comprises a first region adjacent to the first gate structure and a second region adjacent to the second gate structure. A depth of the first region is equal to a depth of the second region.

公开(公告)号：US20250126799A1

公开(公告)日：2025-04-17

申请号：US18673528

申请日：2024-05-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kang-Oh YUN ,  Yunjo LEE ,  Dongjin LEE ,  Jaeduk LEE

IPC: H10B43/40 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27

Abstract: A semiconductor device may include a substrate containing first to third doping regions, first and second gate structures between the first and second doping regions, and a gate separation layer between the first and second gate structures. Each of the first and second gate structures may include a first gate dielectric layer, a first gate conductive layer on the first gate dielectric layer, and a second gate conductive layer between the gate separation layer and the first gate conductive layer. The gate separation layer may include a first sidewall in contact with the first gate structure and a second sidewall in contact with the second gate structure. A top surface of the gate separation layer may be at a same level as a top surface of the second gate conductive layer.