公开(公告)号：US20250040154A1

公开(公告)日：2025-01-30

申请号：US18624857

申请日：2024-04-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hakseon KIM ,  Dongjin LEE ,  Jaeduk LEE ,  Kangoh YUN

IPC: H10B80/00 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27 ,  H10B43/40

Abstract: A semiconductor device includes a peripheral circuit structure; and a cell structure on the peripheral circuit structure, wherein the peripheral circuit structure comprises: a substrate comprising a cell region, a connection region adjacent to the cell region, and a pad region extending around the cell region and the connection region; a first connection structure between the substrate and the cell structure; a first peripheral circuit transistor in the cell region and/or the connection region; and a second peripheral circuit transistor in the pad region, wherein the first connection structure includes a first wiring structure and a dummy structure, the first wiring structure is electrically connected to the first peripheral circuit transistor and/or the second peripheral circuit transistor, and the dummy structure is not directly connected to the first peripheral circuit transistor.

公开(公告)号：US20240324194A1

公开(公告)日：2024-09-26

申请号：US18602778

申请日：2024-03-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dongjin LEE ,  Junhee LIM ,  Hakseon KIM ,  Kangoh YUN ,  Sohyun LEE

IPC: H10B41/35 ,  G11C16/04 ,  H01L25/065 ,  H10B41/10 ,  H10B41/27 ,  H10B41/41 ,  H10B80/00

CPC classification number: H10B41/35 ,  G11C16/0483 ,  H01L25/0652 ,  H10B41/10 ,  H10B41/27 ,  H10B41/41 ,  H10B80/00 ,  H01L2225/06506

Abstract: An integrated circuit device includes a substrate including an active region including a central active region, base active regions and extended active regions integrated together and defined by a device isolation film. A drain region is located in the central active region, and source regions are respectively located in the base active regions. The base active regions are spaced apart from each other in different diagonal directions with respect to the central active region in a plan view. The extended active regions each have an L-shape, connect the central active region and the base active regions, and are spaced apart from each other. Gate structures that respectively cross the base active regions and are spaced apart from each other on the substrate. The central active region, the extended active regions, the base active regions, and the gate structures configure pass transistors, and the pass transistors share the drain region.

公开(公告)号：US20210028283A1

公开(公告)日：2021-01-28

申请号：US16822389

申请日：2020-03-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungkweon BAEK ,  Taeyoung KIM ,  Hakseon KIM ,  Kangoh YUN ,  Changhoon JEON ,  Junhee LIM

IPC: H01L29/10 ,  H01L29/423

Abstract: A semiconductor device includes a gate structure disposed on a substrate. The gate structure has a first sidewall and a second sidewall facing the first sidewall. A first impurity region is disposed within an upper portion of the substrate. The first impurity region is spaced apart from the first sidewall. A third impurity region is within the upper portion of the substrate. The third impurity region is spaced apart from the second sidewall. A first trench is disposed within the substrate between the first sidewall and the first impurity region. The first trench is spaced apart from the first sidewall. A first barrier insulation pattern is disposed within the first trench.