公开(公告)号：US20150187606A1

公开(公告)日：2015-07-02

申请号：US14613179

申请日：2015-02-03

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yukihiro SATO ,  Nobuya KOIKE

IPC: H01L21/56 ,  H01L23/495

CPC classification number: H01L21/561 ,  H01L23/3107 ,  H01L23/4334 ,  H01L23/49503 ,  H01L23/49517 ,  H01L23/49541 ,  H01L23/49575 ,  H01L24/24 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L24/92 ,  H01L25/0657 ,  H01L2224/05554 ,  H01L2224/291 ,  H01L2224/32245 ,  H01L2224/451 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/48463 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/49177 ,  H01L2224/73265 ,  H01L2224/85181 ,  H01L2224/85205 ,  H01L2224/92247 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2924/10162 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/386 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00

Abstract: There is provided a technology enabling the improvement of the reliability of a semiconductor device manufactured by physically fixing separately formed chip mounting portion and lead frame. A feature of an embodiment resides in that, a second junction portion formed in a suspension lead is fitted into a first junction portion formed in a chip mounting portion, thereby to physically fix the chip mounting portion and the suspension lead. Specifically, the first junction portion is formed of a concave part disposed in the surface of the chip mounting portion. The second junction portion forms a part of the suspension lead.

Abstract translation: 提供了一种能够提高通过物理地固定单独形成的芯片安装部分和引线框而制造的半导体器件的可靠性的技术。 实施例的特征在于，形成在悬挂引线中的第二接合部嵌入到形成在芯片安装部分中的第一接合部分中，从而物理地固定芯片安装部分和悬架引线。 具体而言，第一接合部由设置在芯片安装部的表面的凹部形成。 第二接合部分形成悬挂引线的一部分。

公开(公告)号：US20210118781A1

公开(公告)日：2021-04-22

申请号：US17060545

申请日：2020-10-01

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kazunori HASEGAWA ,  Yuichi YATO ,  Hiroyuki NAKAMURA ,  Yukihiro SATO ,  Hiroya SHIMOYAMA

IPC: H01L23/495 ,  H01L23/31 ,  H01L23/00

Abstract: A semiconductor device includes: a semiconductor chip including a field effect transistor for switching; a die pad on which the semiconductor chip is mounted via a first bonding material; a lead electrically connected to a pad for source of the semiconductor chip through a metal plate; a lead coupling portion formed integrally with the lead; and a sealing portion for sealing them. A back surface electrode for drain of the semiconductor chip and the die pad are bonded via the first bonding material, the metal plate and the pad for source of the semiconductor chip are bonded via a second bonding material, and the metal plate and the lead coupling portion are bonded via a third bonding material. The first, second, and third bonding materials have conductivity, and an elastic modulus of each of the first and second bonding materials is lower than that of the third bonding material.

公开(公告)号：US20180122727A1

公开(公告)日：2018-05-03

申请号：US15858493

申请日：2017-12-29

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yukihiro SATO ,  Akira MUTO ,  Ryo KANDA ,  Takamitsu KANAZAWA

IPC: H01L23/495 ,  H01L29/739 ,  H01L23/31 ,  H01L25/075 ,  H01L27/06 ,  H02P27/06

CPC classification number: H01L23/49562 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/49541 ,  H01L23/49575 ,  H01L25/0753 ,  H01L27/0664 ,  H01L29/7397 ,  H01L2224/0603 ,  H01L2224/48137 ,  H01L2224/48139 ,  H01L2224/4903 ,  H01L2224/49111 ,  H02P27/06

Abstract: To improve the reliability of a semiconductor device. A chip mounting portion TAB5 is arranged to be shifted to the +x direction side. Further, a gate electrode pad of a semiconductor chip CHP1 (LV) and a pad of a semiconductor chip CHP3 are electrically coupled by a wire W1a and a wire W1b through a relay lead RL1. Likewise, a gate electrode pad of a semiconductor chip CHP1 (LW) and the pad of the semiconductor chip CHP3 are electrically coupled by a wire W1c and a wire W1d through a relay lead RL2. At this time, the structures of parts of the relay leads RL1 and RL2, which are exposed from a sealing body MR are different from the structures of respective parts exposed from the sealing body MR, of a plurality of leads LD1 and LD2 which function as external terminals.

公开(公告)号：US20170141086A1

公开(公告)日：2017-05-18

申请号：US15420410

申请日：2017-01-31

Applicant: Renesas Electronics Corporation

Inventor： Katsuhiko FUNATSU ,  Yukihiro SATO ,  Takamitsu KANAZAWA ,  Masahiro KOIDO ,  Hiroyoshi TAYA

IPC: H01L25/07 ,  H01L23/10 ,  H01L23/00 ,  H01L29/417 ,  H01L21/54 ,  H01L23/16 ,  H01L23/498 ,  H01L23/053 ,  H01L21/52

CPC classification number: H01L23/49838 ,  H01L21/52 ,  H01L21/54 ,  H01L23/02 ,  H01L23/04 ,  H01L23/053 ,  H01L23/057 ,  H01L23/10 ,  H01L23/12 ,  H01L23/15 ,  H01L23/16 ,  H01L23/3735 ,  H01L23/495 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/498 ,  H01L23/49811 ,  H01L23/49844 ,  H01L24/06 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L25/071 ,  H01L25/072 ,  H01L29/41708 ,  H01L2224/05553 ,  H01L2224/0603 ,  H01L2224/29101 ,  H01L2224/32225 ,  H01L2224/45014 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48101 ,  H01L2224/48106 ,  H01L2224/4813 ,  H01L2224/48227 ,  H01L2224/4846 ,  H01L2224/48472 ,  H01L2224/49111 ,  H01L2224/49113 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/1304 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H02S40/32 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/014 ,  H01L2224/85399

Abstract: A semiconductor device includes a plurality of metal patterns formed on a ceramic substrate, and a semiconductor chip mounted on some of the plurality of metal patterns. Also, a plurality of hollow portions are formed in peripheral portions of the plurality of metal patterns. In addition, the plurality of hollow portions are not formed in a region overlapping the semiconductor chip in the plurality of metal patterns. Furthermore, the plurality of hollow portions are provided in a plurality of metal patterns arranged at a position closest to the peripheral portion of the top surface of the ceramic substrate among the plurality of metal patterns.

公开(公告)号：US20170033035A1

公开(公告)日：2017-02-02

申请号：US15174568

申请日：2016-06-06

Applicant: Renesas Electronics Corporation

Inventor： Yukihiro SATO ,  Akira MUTO ,  Ryo KANDA ,  Takamitsu KANAZAWA

IPC: H01L23/495 ,  H01L29/739 ,  H01L27/06 ,  H01L23/31

CPC classification number: H01L23/49562 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/49541 ,  H01L23/49575 ,  H01L25/0753 ,  H01L27/0664 ,  H01L29/7397 ,  H01L2224/0603 ,  H01L2224/48137 ,  H01L2224/48139 ,  H01L2224/4903 ,  H01L2224/49111 ,  H02P27/06

Abstract: To improve the reliability of a semiconductor device. A chip mounting portion TAB5 is arranged to be shifted to the +x direction side. Further, a gate electrode pad of a semiconductor chip CHP1 (LV) and a pad of a semiconductor chip CHP3 are electrically coupled by a wire W1a and a wire W1b through a relay lead RL1. Likewise, a gate electrode pad of a semiconductor chip CHP1 (LW) and the pad of the semiconductor chip CHP3 are electrically coupled by a wire W1c and a wire W1d through a relay lead RL2. At this time, the structures of parts of the relay leads RL1 and RL2, which are exposed from a sealing body MR are different from the structures of respective parts exposed from the sealing body MR, of a plurality of leads LD1 and LD2 which function as external terminals.

Abstract translation: 提高半导体器件的可靠性。 芯片安装部TAB5布置成向+ x方向侧移动。 此外，半导体芯片CHP1（LV）的栅电极焊盘和半导体芯片CHP3的焊盘通过导线W1a和导线W1b通过继电器引线RL1电耦合。 同样地，半导体芯片CHP1（LW）的栅电极焊盘和半导体芯片CHP3的焊盘通过引线W1c和引线W1d通过继电器引线RL2电耦合。 此时，从密封体MR露出的继电器引线RL1，RL2的部分的结构与作为密封体MR的多个引线LD1，LD2的密封体MR露出的各部分的结构不同 外部端子。

公开(公告)号：US20160093589A1

公开(公告)日：2016-03-31

申请号：US14863837

申请日：2015-09-24

Applicant: Renesas Electronics Corporation

Inventor： Yukihiro SATO ,  Katsuhiko FUNATSU ,  Takamitsu KANAZAWA ,  Masahiro KOIDO ,  Hiroyoshi TAYA

IPC: H01L25/065 ,  H01L23/00

CPC classification number: H01L25/0655 ,  H01L21/4846 ,  H01L23/049 ,  H01L23/24 ,  H01L23/3735 ,  H01L23/49838 ,  H01L23/49844 ,  H01L23/49861 ,  H01L24/09 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L25/072 ,  H01L25/16 ,  H01L25/18 ,  H01L2224/0603 ,  H01L2224/0905 ,  H01L2224/32225 ,  H01L2224/45014 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2224/4846 ,  H01L2224/48472 ,  H01L2224/49111 ,  H01L2224/49113 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/16151 ,  H01L2924/16251 ,  H01L2924/181 ,  H02M7/219 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014

Abstract: Reduction in reliability of a semiconductor device is suppressed. A semiconductor device includes a plurality of metal patterns formed on a ceramic substrate, and a plurality of semiconductor chips mounted on the plurality of metal patterns. Also, the plurality of metal patterns include metal patterns MPH and MPU which face each other. In addition, a region which is provided between these metal patterns MPH and MPU and which is exposed from the plurality of metal patterns extends so as to zigzag along an extending direction of the metal pattern MPH.

Abstract translation: 抑制半导体器件的可靠性降低。 半导体器件包括形成在陶瓷衬底上的多个金属图案和安装在多个金属图案上的多个半导体芯片。 此外，多个金属图案包括彼此面对的金属图案MPH和MPU。 此外，设置在这些金属图案MPH和MPU之间并且从多个金属图案露出的区域沿着金属图案MPH的延伸方向延伸成锯齿状。

公开(公告)号：US20150325506A1

公开(公告)日：2015-11-12

申请号：US14805218

申请日：2015-07-21

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yukihiro SATO ,  Nobuya KOIKE

IPC: H01L23/495 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L21/561 ,  H01L23/3107 ,  H01L23/4334 ,  H01L23/49503 ,  H01L23/49517 ,  H01L23/49541 ,  H01L23/49575 ,  H01L24/24 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L24/92 ,  H01L25/0657 ,  H01L2224/05554 ,  H01L2224/291 ,  H01L2224/32245 ,  H01L2224/451 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/48463 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/49177 ,  H01L2224/73265 ,  H01L2224/85181 ,  H01L2224/85205 ,  H01L2224/92247 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2924/10162 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/386 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00

Abstract: There is provided a technology enabling the improvement of the reliability of a semiconductor device manufactured by physically fixing separately formed chip mounting portion and lead frame. A feature of an embodiment resides in that, a second junction portion formed in a suspension lead is fitted into a first junction portion formed in a chip mounting portion, thereby to physically fix the chip mounting portion and the suspension lead. Specifically, the first junction portion is formed of a concave part disposed in the surface of the chip mounting portion. The second junction portion forms a part of the suspension lead.

公开(公告)号：US20140061821A1

公开(公告)日：2014-03-06

申请号：US13973077

申请日：2013-08-22

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kenya KAWANO ,  Hiroyuki NAKAMURA ,  Yukihiro SATO

IPC: H01L23/373 ,  H01L29/772

CPC classification number: H01L23/373 ,  H01L23/49513 ,  H01L23/49537 ,  H01L23/49548 ,  H01L23/49551 ,  H01L23/49568 ,  H01L23/49575 ,  H01L23/49582 ,  H01L24/29 ,  H01L24/32 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/84 ,  H01L29/772 ,  H01L29/7813 ,  H01L2224/05553 ,  H01L2224/29101 ,  H01L2224/29339 ,  H01L2224/32245 ,  H01L2224/37013 ,  H01L2224/371 ,  H01L2224/37124 ,  H01L2224/37147 ,  H01L2224/4007 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/73221 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/84801 ,  H01L2924/014 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/18301 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: Provided is an electronic device having a semiconductor device and a mounting board. The semiconductor device has a die pad, a semiconductor chip on the die pad, a coupling member coupling the die pad to the semiconductor chip, and a semiconductor package member covering the upper portion of the semiconductor chip and the side surface of the die pad. In this semiconductor device, the plane area of the coupling member coupling the mounting board to the die pad is smaller than the plane area of the lower surface of the die pad exposed from the semiconductor package material. This makes it possible to reduce separation between the die pad and the semiconductor chip resulting from cracks, due to temperature cycling, of the coupling member present between the die pad and the semiconductor chip.

Abstract translation: 提供一种具有半导体器件和安装板的电子器件。 半导体器件具有管芯焊盘，管芯焊盘上的半导体芯片，将管芯焊盘连接到半导体芯片的耦合部件以及覆盖半导体芯片的上部和管芯焊盘侧表面的半导体封装件。 在该半导体器件中，将安装板耦合到管芯焊盘的耦合部件的平面面积小于从半导体封装材料露出的裸片焊盘的下表面的平面面积。 这使得可以减少由于存在于管芯焊盘和半导体芯片之间的耦合部件的温度循环而导致的芯片焊盘和半导体芯片之间的分离。