公开(公告)号：US11302828B2

公开(公告)日：2022-04-12

申请号：US17084163

申请日：2020-10-29

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Digh Hisamoto ,  Yoshiyuki Kawashima ,  Takashi Hashimoto

IPC: H01L29/792 ,  H01L27/11568 ,  H01L29/78 ,  H01L27/092

Abstract: A semiconductor device includes a memory cell which is configured of a FinFET having a split-gate type MONOS structure, the FinFET has a plurality of source regions formed in a plurality of fins, and the plurality of source regions are commonly connected by a source line contact. Further, the FinFET has a plurality of drain regions formed in the plurality of fins, the plurality of drain regions are commonly connected by a bit line contact, and the FinFET constitutes a memory cell of 1 bit.

公开(公告)号：US10910394B2

公开(公告)日：2021-02-02

申请号：US16881484

申请日：2020-05-22

Applicant: Renesas Electronics Corporation

Inventor： Tsutomu Okazaki ,  Akira Kato ,  Kan Yasui ,  Kyoya Nitta ,  Digh Hisamoto ,  Yasushi Ishii ,  Daisuke Okada ,  Toshihiro Tanaka ,  Toshikazu Matsui

IPC: H01L27/1157 ,  H01L27/105 ,  H01L29/423 ,  H01L21/28 ,  G11C16/04 ,  H01L27/02 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/66 ,  H01L29/792 ,  H01L29/06 ,  H01L29/51

Abstract: A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section.

公开(公告)号：US10692878B2

公开(公告)日：2020-06-23

申请号：US16552524

申请日：2019-08-27

Applicant: Renesas Electronics Corporation

Inventor： Tsutomu Okazaki ,  Akira Kato ,  Kan Yasui ,  Kyoya Nitta ,  Digh Hisamoto ,  Yasushi Ishii ,  Daisuke Okada ,  Toshihiro Tanaka ,  Toshikazu Matsui

IPC: H01L27/1157 ,  H01L27/105 ,  H01L29/423 ,  H01L21/28 ,  G11C16/04 ,  H01L27/02 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/66 ,  H01L29/792 ,  H01L29/06 ,  H01L29/51

Abstract: A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section.

公开(公告)号：US10141324B2

公开(公告)日：2018-11-27

申请号：US15581576

申请日：2017-04-28

Applicant: Renesas Electronics Corporation

Inventor： Tsutomu Okazaki ,  Daisuke Okada ,  Kyoya Nitta ,  Toshihiro Tanaka ,  Akira Kato ,  Toshikazu Matsui ,  Yasushi Ishii ,  Digh Hisamoto ,  Kan Yasui

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/792 ,  H01L27/1157 ,  H01L29/51 ,  H01L27/02 ,  H01L21/28

Abstract: A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section.

公开(公告)号：US09589638B2

公开(公告)日：2017-03-07

申请号：US15152391

申请日：2016-05-11

Applicant: Renesas Electronics Corporation

Inventor： Tsuyoshi Arigane ,  Daisuke Okada ,  Digh Hisamoto

IPC: G11C16/04 ,  G11C16/14 ,  H01L29/423 ,  H01L27/115 ,  H01L29/51 ,  G11C16/34

CPC classification number: G11C16/0466 ,  G11C16/0483 ,  G11C16/14 ,  G11C16/344 ,  H01L27/11568 ,  H01L27/1157 ,  H01L29/42344 ,  H01L29/511 ,  H01L29/518 ,  H01L29/792

Abstract: A first potential and a second potential lower than the first potential are applied to a first end of a memory gate electrode part of the nonvolatile memory and to a second end of the memory gate electrode part, respectively, so that a current is caused to flow in a direction in which the memory gate electrode part extends, then, a hole is injected from the memory gate electrode part into a charge accumulating part below it, therefore, an electron accumulated in the charge accumulating part is eliminated. By causing the current to flow through the memory gate electrode part of a memory cell region as described above, Joule heat can be generated to heat the memory cell. Consequently, in the erasing by a FN tunneling method in which the erasing characteristics degrade at a low temperature, the erasing speed can be improved by heating the memory gate electrode part.

Abstract translation: 低于第一电位的第一电势和第二电位被分别施加到非易失性存储器的存储栅电极部分的第一端和存储栅电极部分的第二端，使得电流流过 在存储栅电极部分延伸的方向上，从存储栅电极部分注入空穴到其下方的电荷累积部分，因此，积累在电荷累积部分中的电子被消除。 通过使电流流过如上所述的存储单元区域的存储栅电极部分，可以产生焦耳热以加热存储单元。 因此，在擦除特性在低温下劣化的FN隧穿法的擦除中，通过加热存储栅电极部分可以提高擦除速度。

公开(公告)号：US08816426B2

公开(公告)日：2014-08-26

申请号：US13845005

申请日：2013-03-17

Applicant: Renesas Electronics Corporation

Inventor： Itaru Yanagi ,  Toshiyuki Mine ,  Hirotaka Hamamura ,  Digh Hisamoto ,  Yasuhiro Shimamoto

IPC: H01L29/792

CPC classification number: H01L29/792 ,  G11C16/0466 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/42344 ,  H01L29/513

Abstract: In a non-volatile memory, writing/erasing is performed by changing a total charge amount by injecting electrons and holes into a silicon nitride film, which serves as a charge accumulation layer. The gate electrode of a memory cell has a laminated structure made of a plurality of polysilicon films with different impurity concentrations. In a two-layered structure the gate electrode has a p-type polysilicon film with a low impurity concentration and a p+-type polysilicon film with a high impurity concentration deposited thereon. Holes are injected into the charge accumulation layer from the gate electrode.

Abstract translation: 在非易失性存储器中，通过将电子和空穴注入用作电荷累积层的氮化硅膜中来改变总电荷量来进行写/擦除。 存储单元的栅电极具有由具有不同杂质浓度的多个多晶硅膜制成的叠层结构。 在两层结构中，栅电极具有杂质浓度低的p型多晶硅膜和沉积有高杂质浓度的p +型多晶硅膜。 孔从栅电极注入电荷累积层。

公开(公告)号：US10818679B2

公开(公告)日：2020-10-27

申请号：US16460476

申请日：2019-07-02

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Digh Hisamoto ,  Yoshiyuki Kawashima

IPC: H01L27/11521 ,  H01L21/8234 ,  H01L27/1158 ,  H01L27/11565 ,  H01L27/11568

Abstract: In a MONOS memory of the split-gate type formed by a field effect transistor formed on a fin, it is prevented that the rewrite lifetime of the MONOS memory is reduced due to charges being locally transferred into and out of an ONO film in the vicinity of the top of the fin by repeating the write operation and the erase operation. By forming a source region at a position spaced downward from a first upper surface of the fin in a region directly below a memory gate electrode, the current is prevented from flowing concentratedly at the upper end of the fin.

公开(公告)号：US10147488B2

公开(公告)日：2018-12-04

申请号：US15640568

申请日：2017-07-02

Applicant: Renesas Electronics Corporation

Inventor： Digh Hisamoto

IPC: H01L27/115 ,  G11C16/10 ,  G11C16/24 ,  G11C16/30 ,  G11C8/08 ,  G11C16/04 ,  G11C16/08 ,  G11C16/14 ,  G11C16/16 ,  G11C16/26 ,  G11C16/32 ,  G11C16/34 ,  H01L29/78

Abstract: Provided is a semiconductor device including nonvolatile memory cells each including a FinFET having excellent memory characteristics. The semiconductor device includes a semiconductor substrate, memory cells each formed in the semiconductor substrate and having a split-gate structure including an opposed-gate selection gate electrode, a memory gate electrode, and a pair of terminals, and a word line driver circuit which supplies a selection voltage to a selection gate electrode of the selected one of the memory cells and supplies a non-selection voltage to the selection gate electrode of the non-selected one of the memory cells. The word line driver circuit supplies, as the non-selection voltage, a voltage which is negative or positive relative to a potential in the semiconductor substrate so as to bring a selection transistor corresponding to the selection gate electrode of the non-selected memory cell into an OFF state.

公开(公告)号：US09640546B2

公开(公告)日：2017-05-02

申请号：US14609659

申请日：2015-01-30

Applicant: Renesas Electronics Corporation

Inventor： Tsutomu Okazaki ,  Daisuke Okada ,  Kyoya Nitta ,  Toshihiro Tanaka ,  Akira Kato ,  Toshikazu Matsui ,  Yasushi Ishii ,  Digh Hisamoto ,  Kan Yasui

IPC: H01L29/792 ,  H01L27/1157 ,  H01L27/105 ,  H01L29/423 ,  G11C16/04 ,  H01L21/28 ,  H01L27/02 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/66

CPC classification number: H01L27/1157 ,  G11C16/0425 ,  H01L21/28282 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/0649 ,  H01L29/4234 ,  H01L29/42344 ,  H01L29/518 ,  H01L29/66833 ,  H01L29/792

Abstract: A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section.

公开(公告)号：US09515082B2

公开(公告)日：2016-12-06

申请号：US14664493

申请日：2015-03-20

Applicant: Renesas Electronics Corporation

Inventor： Tsuyoshi Arigane ,  Digh Hisamoto ,  Daisuke Okada

IPC: H01L21/336 ,  H01L27/115 ,  H01L29/792 ,  H01L29/66 ,  H01L29/423 ,  H01L21/28 ,  H01L21/762

CPC classification number: H01L27/11568 ,  H01L21/28282 ,  H01L21/76224 ,  H01L21/76229 ,  H01L29/42344 ,  H01L29/66545 ,  H01L29/66833 ,  H01L29/792

Abstract: A memory gate is formed of a first memory gate including a second gate insulating film made of a second insulating film and a first memory gate electrode, and a second memory gate including a third gate insulating film made of a third insulating film and a second memory gate electrode. In addition, the lower surface of the second memory gate electrode is located lower in level than the lower surface of the first memory gate electrode. As a result, during an erase operation, an electric field is concentrated on the corner portion of the first memory gate electrode which is located closer to a selection gate and a semiconductor substrate and on the corner portion of the second memory gate electrode which is located closer to the first memory gate and the semiconductor substrate. This allows easy injection of holes into each of the second and third insulating films.

Abstract translation: 存储栅极由包括由第二绝缘膜和第一存储栅电极构成的第二栅绝缘膜的第一存储栅形成，以及包括由第三绝缘膜和第二存储器构成的第三栅绝缘膜的第二存储栅 栅电极。 此外，第二存储栅电极的下表面位于比第一存储栅电极的下表面更低的电平。 结果，在擦除操作期间，电场集中在位于更靠近选择栅极和半导体衬底的位于第一存储栅电极的角部上，并且位于位于第二存储栅电极的拐角部分 更靠近第一存储器栅极和半导体衬底。 这允许容易地将孔注入到每个第二和第三绝缘膜中。