公开(公告)号：US20190221645A1

公开(公告)日：2019-07-18

申请号：US16288558

申请日：2019-02-28

Applicant: QUALCOMM Incorporated

Inventor： Ye LU ,  Junjing BAO ,  Bin YANG ,  Lixin GE ,  Yun YUE

IPC: H01L29/16 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L29/72 ,  H01L29/10

CPC classification number: H01L29/1606 ,  H01L21/02115 ,  H01L21/02181 ,  H01L21/02271 ,  H01L29/1004 ,  H01L29/1608 ,  H01L29/66037 ,  H01L29/66068 ,  H01L29/6656 ,  H01L29/72 ,  H01L29/785

Abstract: An integrated circuit (IC) device may include a semiconductor structure. The semiconductor structure may include a source contact, a drain contact, and a gate. A first fluorocarbon spacer may be between the gate and the source contact. A second fluorocarbon spacer may be between the gate and the drain contact.

公开(公告)号：US20190027576A1

公开(公告)日：2019-01-24

申请号：US15710271

申请日：2017-09-20

Applicant: QUALCOMM Incorporated

Inventor： Bin YANG ,  Xia LI ,  Gengming TAO

IPC: H01L29/66 ,  H01L29/778

Abstract: A metal-oxide-semiconductor field effect transistor (MOSFET) device may include a substrate. A composite multilayer channel material may be on the substrate. The composite multilayer channel material may include a channel region, a source region, and a drain region. A gate may be on the channel region of the composite multilayer channel material.

公开(公告)号：US20180254194A1

公开(公告)日：2018-09-06

申请号：US15450605

申请日：2017-03-06

Applicant: QUALCOMM Incorporated

Inventor： Xia LI ,  Bin YANG ,  Gengming TAO

IPC: H01L21/322 ,  H01L23/31 ,  H01L23/29 ,  H01L21/02

Abstract: An integrated circuit (IC) device may include a substrate having an active device layer. The integrated circuit may also include a first defect layer. The first defect layer may have a first surface facing a backside of the active device layer. The integrated circuit may further include a second defect layer. The second defect layer may face a second surface opposite the first surface of the first defect layer.

公开(公告)号：US20160336324A1

公开(公告)日：2016-11-17

申请号：US14713712

申请日：2015-05-15

Applicant: QUALCOMM Incorporated

Inventor： Xia LI ,  Bin YANG

IPC: H01L27/092 ,  H01L29/10 ,  H01L21/265 ,  H01L21/02 ,  H01L29/78 ,  H01L29/423 ,  H01L21/8238 ,  H01L27/088 ,  H01L29/66

CPC classification number: H01L27/0928 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/823814 ,  H01L21/823885 ,  H01L21/823892 ,  H01L27/088 ,  H01L27/092 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/66356 ,  H01L29/66977 ,  H01L29/7391

Abstract: A vertically integrated transistor device increases the effective active area of the device to improve the performance characteristics of the device. The transistor device may include a plurality of gate elements, a plurality of source-drain elements extending parallel to the plurality of gate elements and horizontally spaced therefrom; and a plurality of fin elements extending parallel to the plurality of gate elements and vertically spaced therefrom, wherein each of the plurality of fin elements is horizontally spaced a first distance from each of the other ones of the plurality of fin elements.

Abstract translation: 垂直集成的晶体管器件增加了器件的有效有效面积，以提高器件的性能特性。 晶体管器件可以包括多个栅极元件，多个源极 - 漏极元件，其平行于多个栅极元件延伸并与之水平间隔开; 以及与所述多个栅极元件平行延伸并且与其垂直间隔开的多个翅片元件，其中所述多个翅片元件中的每一个与所述多个翅片元件中的每一个中的每一个水平间隔开第一距离。

公开(公告)号：US20160005849A1

公开(公告)日：2016-01-07

申请号：US14321539

申请日：2014-07-01

Applicant: QUALCOMM Incorporated

Inventor： Xia LI ,  Bin YANG ,  Ming CAI

IPC: H01L29/778 ,  H01L29/66 ,  H01L21/02 ,  H01L29/201 ,  H01L29/205 ,  H01L21/762 ,  H01L29/78 ,  H01L29/20

CPC classification number: H01L29/7789 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/02507 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/76224 ,  H01L29/0657 ,  H01L29/151 ,  H01L29/20 ,  H01L29/201 ,  H01L29/205 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/66522 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7781 ,  H01L29/7783 ,  H01L29/7785 ,  H01L29/7787 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/78696

Abstract: An inner fin of a high bandgap material is on a substrate, having two vertical faces, and is surrounded by a carrier redistribution fin of a low bandgap material. The inner fin and the carrier redistribution fin have two vertical interfaces. The carrier redistribution fin has a thickness and a bandgap relative to the bandgap of the inner fin that establishes, along the two vertical interfaces, an equilibrium of a corresponding two two-dimensional electron gasses.

公开(公告)号：US20210233959A1

公开(公告)日：2021-07-29

申请号：US16752288

申请日：2020-01-24

Applicant: QUALCOMM Incorporated

Inventor： Bin YANG ,  Xia LI ,  Gengming TAO

IPC: H01L27/24 ,  H01L45/00

Abstract: Certain aspects of the present disclosure generally relate to a vertically stacked multilayer resistive random access memory (RRAM) and methods for fabricating such an RRAM. The vertically stacked multilayer RRAM generally includes a planar substrate layer and a plurality of metal-insulator-metal (MIM) stacks, each MIM stack structure of the plurality of MIM stacks comprising a plurality of MIM structures extending orthogonally above the planar substrate.

公开(公告)号：US20200052078A1

公开(公告)日：2020-02-13

申请号：US16660006

申请日：2019-10-22

Applicant: QUALCOMM Incorporated

Inventor： Gengming TAO ,  Bin YANG ,  Xia LI

IPC: H01L29/417 ,  H01L29/08 ,  H01L21/308 ,  H01L21/306 ,  H01L29/66 ,  H01L29/45 ,  H01L21/285 ,  H01L29/10 ,  H01L29/205 ,  H01L29/737

Abstract: In certain aspects, a heterojunction bipolar transistor (HBT) comprises a collector mesa, a base mesa on the collector mesa, and an emitter mesa on the base mesa. The base mesa has a tapered sidewall tapering from a wide bottom to a narrow top. The HBT further comprises a collector contact on a portion of the collector mesa and extending to a portion of the tapered sidewall of the base mesa.

公开(公告)号：US20190229933A1

公开(公告)日：2019-07-25

申请号：US15877630

申请日：2018-01-23

Applicant: QUALCOMM Incorporated

Inventor： Xia LI ,  Seung Hyuk KANG ,  Bin YANG ,  Gengming TAO

IPC: H04L9/32 ,  G06F11/10 ,  G06F21/31 ,  G06F3/06 ,  G11C13/00 ,  G11C29/52

Abstract: In certain aspects, an apparatus comprises a plurality of PUF cells. Each PUF cell comprises a first transistor in series with a first loading resistive component and coupled to a common cross-coupled node and cross-coupled to a complementary common cross-coupled node, a second transistor in series with a second loading resistive component and coupled to the complementary common cross-coupled node and cross-coupled to the common cross-coupled node, a first pass-gate and a second pass-gate coupled to a bit line and the complementary bit line, respectively. The apparatus further comprises an auxiliary peripheral circuit coupled to the bit line, the complementary bit line, the common cross-coupled node, and the complementary common cross-coupled node. During activation, the selected PUF cell, together with the auxiliary peripheral circuit, forms a cross-coupled inverter pair and outputs a physical unclonable function value.

公开(公告)号：US20190189787A1

公开(公告)日：2019-06-20

申请号：US15985423

申请日：2018-05-21

Applicant: QUALCOMM Incorporated

Inventor： Gengming TAO ,  Xia LI ,  Bin YANG

IPC: H01L29/737 ,  H01L29/08 ,  H01L29/423 ,  H01L29/417 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L29/7371 ,  H01L21/31058 ,  H01L21/31138 ,  H01L21/76885 ,  H01L23/528 ,  H01L23/53295 ,  H01L29/0817 ,  H01L29/0821 ,  H01L29/41708 ,  H01L29/42304

Abstract: A heterojunction bipolar transistor (HBT) may include a base contact and emitter mesas on a collector mesa. The HBT may include emitter contacts on the emitter mesas. The HBT may include a first dielectric layer on the collector mesa, sidewalls of the emitter mesas, and the base contact. The HBT may further include a second dielectric layer on the first dielectric layer and on sidewalls of the emitter contacts. The HBT may further include a secondary conductive layer on the first dielectric layer, the second dielectric layer, and the emitter contacts.

公开(公告)号：US20190103459A1

公开(公告)日：2019-04-04

申请号：US15724147

申请日：2017-10-03

Applicant: QUALCOMM Incorporated

Inventor： Ye LU ,  Junjing BAO ,  Bin YANG

IPC: H01L49/02 ,  H01L21/321 ,  H01L21/768 ,  H01L27/11502 ,  H01L29/66 ,  H01L27/108

Abstract: A capacitor may include a first conductive layer forming a first capacitor plate, a second conductive layer forming a second capacitor plate, and a first insulating material on the first conductive layer. The first insulating material may include a positive capacitance material. The capacitor may further include a second insulating material disposed over the first insulating material and between the first insulating material and the second conductive layer. The second insulating material may include a negative capacitance ferroelectric material.