公开(公告)号：US20150071430A1

公开(公告)日：2015-03-12

申请号：US14072599

申请日：2013-11-05

Applicant: QUALCOMM Incorporated

Inventor： Xiaochun Zhu ,  Steven M. Millendorf ,  Xu Guo ,  David M. Jacobson ,  Kangho Lee ,  Seung H. Kang ,  Matthew Michael Nowak

IPC: G11C11/16 ,  H04L9/30

CPC classification number: G11C11/1673 ,  G09C1/00 ,  G11C11/161 ,  H04L9/0866 ,  H04L9/30 ,  H04L9/3278

Abstract: One feature pertains to a method for implementing a physically unclonable function (PUF). The method includes providing an array of magnetoresistive random access memory (MRAM) cells, where the MRAM cells are each configured to represent one of a first logical state and a second logical state. The array of MRAM cells are un-annealed and free from exposure to an external magnetic field oriented in a direction configured to initialize the MRAM cells to a single logical state of the first and second logical states. Consequently, each MRAM cell has a random initial logical state of the first and second logical states. The method further includes sending a challenge to the MRAM cell array that reads logical states of select MRAM cells of the array, and obtaining a response to the challenge from the MRAM cell array that includes the logical states of the selected MRAM cells of the array.

Abstract translation: 一个特征涉及用于实现物理不可克隆功能（PUF）的方法。 该方法包括提供磁阻随机存取存储器（MRAM）单元阵列，其中MRAM单元被配置为表示第一逻辑状态和第二逻辑状态之一。 MRAM单元的阵列是未退火的，并且没有暴露于被配置为将MRAM单元初始化的方向定向到第一和第二逻辑状态的单个逻辑状态的外部磁场。 因此，每个MRAM单元具有第一和第二逻辑状态的随机初始逻辑状态。 该方法还包括向MRAM单元阵列发送挑战，该MRAM单元阵列读取阵列的选择MRAM单元的逻辑状态，以及从包括阵列的所选MRAM单元的逻辑状态的MRAM单元阵列获得对挑战的响应。

公开(公告)号：US08969984B2

公开(公告)日：2015-03-03

申请号：US14048704

申请日：2013-10-08

Applicant: QUALCOMM Incorporated

Inventor： Xiaochun Zhu ,  Seung Hyuk Kang ,  Xia Li ,  Kangho Lee

IPC: H01L43/02 ,  H01L43/08 ,  H01L43/12 ,  H01L43/10 ,  H01L27/22

CPC classification number: H01L43/02 ,  H01L27/222 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

Abstract: A magnetic tunnel junction device includes a Synthetic Anti-Ferromagnetic (SAF) layer, a first free layer, and second free layer. The magnetic tunnel junction device further includes a spacer layer between the first and second free layers. The first free layer is magneto-statically coupled to the second free layer. A thickness of the spacer layer is at least 4 Angstroms.

Abstract translation: 磁性隧道结装置包括合成反铁磁（SAF）层，第一自由层和第二自由层。 磁性隧道结装置还包括在第一和第二自由层之间的间隔层。 第一自由层被磁静态耦合到第二自由层。 间隔层的厚度至少为4埃。

公开(公告)号：US08865481B2

公开(公告)日：2014-10-21

申请号：US14172208

申请日：2014-02-04

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Xiaochun Zhu ,  Seung Hyuk Kang

IPC: H01L29/82 ,  B82Y10/00 ,  H01L43/08 ,  H01L43/12 ,  H01L27/22

CPC classification number: H01L43/12 ,  B82Y10/00 ,  G11C11/161 ,  H01L27/228 ,  H01L43/08

Abstract: A semiconductor device includes a magnetic tunnel junction (MTJ) storage element configured to be disposed in a common interlayer metal dielectric (IMD) layer with a logic element. Cap layers separate the common IMD layer from a top and bottom IMD layer. Top and bottom electrodes are coupled to the MTJ storage element. Metal connections to the electrodes are formed in the top and bottom IMD layers respectively through vias in the separating cap layers. Alternatively, the separating cap layers are recessed and the bottom electrodes are embedded, such that direct contact to metal connections in the bottom IMD layer is established. Metal connections to the top electrode in the common IMD layer are enabled by isolating the metal connections from the MTJ storage elements with metal islands and isolating caps.

Abstract translation: 半导体器件包括被配置为设置在具有逻辑元件的公共层间金属电介质（IMD）层中的磁隧道结（MTJ）存储元件。 盖层将公共IMD层与顶部和底部IMD层分开。 顶部和底部电极耦合到MTJ存储元件。 金属与电极的连接分别通过分离盖层中的通孔形成在顶部和底部IMD层中。 或者，分离盖层是凹进的并且底部电极被嵌入，从而建立与底部IMD层中的金属连接的直接接触。 通过用金属岛和隔离帽隔离与MTJ存储元件的金属连接来实现与公共IMD层中顶部电极的金属连接。

公开(公告)号：US08797792B2

公开(公告)日：2014-08-05

申请号：US14022364

申请日：2013-09-10

Applicant: QUALCOMM Incorporated

Inventor： Hari M. Rao ,  Jung Pil Kim ,  Seung H. Kang ,  Xiaochun Zhu ,  Tae Hyun Kim ,  Kangho Lee ,  Xia Li ,  Wah Nam Hsu ,  Wuyang Hao ,  Jungwon Suh ,  Nicholas K. Yu ,  Matthew Michael Nowak ,  Steven M. Millendorf ,  Asaf Ashkenazi

IPC: G11C11/00 ,  G11C11/16 ,  G11C11/14 ,  G11C17/02 ,  G11C17/16 ,  G11C29/02

CPC classification number: G11C11/16 ,  G11C11/14 ,  G11C11/1655 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C17/02 ,  G11C17/16 ,  G11C29/027

Abstract: A memory device includes a magnetic tunnel junction (MTJ) bitcell. The MTJ bitcell includes a first MTJ and a second MTJ. The memory device further includes programming circuitry configured to generate a non-reversible state at the bitcell by applying a program signal to a selected one of the first MTJ and the second MTJ of the bitcell. The non-reversible state corresponds to a value of the MTJ bitcell that is determined by comparing a first value read at the first MTJ and a second value read at the second MTJ.

Abstract translation: 存储器件包括磁性隧道结（MTJ）位单元。 MTJ位单元包括第一MTJ和第二MTJ。 存储器件还包括编程电路，其被配置为通过将程序信号施加到位单元的第一MTJ和第二MTJ中的所选择的一个来在位单元处产生不可逆状态。 不可逆状态对应于通过比较在第一MTJ读取的第一值和在第二MTJ读取的第二值确定的MTJ比特单元的值。

公开(公告)号：US20140203381A1

公开(公告)日：2014-07-24

申请号：US13748979

申请日：2013-01-24

Applicant: QUALCOMM INCORPORATED

Inventor： Xiaochun Zhu ,  Xia Li ,  Wei-Chuan Chen ,  Seung H. Kang

IPC: H01L43/12 ,  H01L43/02

CPC classification number: H01L43/12 ,  H01L43/08

Abstract: Material surrounding a magnetic tunnel junction (MTJ) device region of a multi-layer starting structure is etched, forming an MTJ device pillar having an MTJ layer with a chemically damaged peripheral edge region. De-nitridation or de-oxidation, or both, restore the chemically damaged peripheral region to form an edge-restored MTJ layer. An MTJ edge restoration assist layer is formed on the edge-restored MTJ layer. An MTJ-edge-protect layer is formed on the insulating MTJ-edge-restoration-assist layer.

Abstract translation: 蚀刻围绕多层起始结构的磁性隧道结（MTJ）器件区域的材料，形成具有化学损伤的外围边缘区域的MTJ层的MTJ器件柱。 脱氮或脱氧，或两者恢复化学损伤的外围区域，形成边缘恢复的MTJ层。 在边缘恢复的MTJ层上形成MTJ边缘恢复辅助层。 在绝缘MTJ边缘恢复辅助层上形成MTJ边缘保护层。

公开(公告)号：US20140108478A1

公开(公告)日：2014-04-17

申请号：US13651954

申请日：2012-10-15

Applicant: QUALCOMM INCORPORATED

Inventor： Kangho Lee ,  Taehyun Kim ,  Xiaochun Zhu ,  David M. Jacobson ,  Raghu Sagar Madala ,  Wenqing Wu ,  Jung Pill Kim ,  Seung H. Kang

IPC: G06F7/58

CPC classification number: G06F7/588

Abstract: A random number generator system that utilizes a magnetic tunnel junction (MTJ) that is controlled by an STT-MTJ entropy controller that determines whether to proceed with generating random numbers or not by monitoring the health of the MTJ-based random number generator is illustrated. If the health of the random number generation is above a threshold, the STT-MTJ entropy controller shuts down the MTJ-based random number generator and sends a message to a requesting chipset that a secure key generation is not possible. If the health of the random number generation is below a threshold, the entropy controller allows the MTJ-based random number generator to generate random numbers based on a specified algorithm, the output of which is post processed and used by a cryptographic-quality deterministic random bit generator to generate a security key for a requesting chipset.

Abstract translation: 示出了利用由STT-MTJ熵控制器控制的磁隧道结（MTJ）的随机数发生器系统，其通过监测基于MTJ的随机数发生器的健康来确定是否继续生成随机数。 如果随机数生成的健康状况高于阈值，则STT-MTJ熵控制器关闭基于MTJ的随机数生成器，并且向请求芯片组发送消息，即不可能产生安全密钥。 如果随机数生成的健康状况低于阈值，则熵控制器允许基于MTJ的随机数发生器基于指定的算法产生随机数，其输出被后处理并由加密质量确定性随机使用 以产生请求芯片组的安全密钥。

公开(公告)号：US20140015077A1

公开(公告)日：2014-01-16

申请号：US14027503

申请日：2013-09-16

Applicant: QUALCOMM Incorporated

Inventor： Kangho Lee ,  Seung H. Kang ,  Xiaochun Zhu

IPC: H01L43/02

CPC classification number: H01L43/08 ,  G06F17/5068 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1675 ,  H01L43/02 ,  H01L43/12

Abstract: A memory cell comprises a magnetic tunnel junction (MTJ) structure that includes a free layer coupled to a bit line and a pinned layer. A magnetic moment of the free layer is substantially parallel to a magnetic moment of the pinned layer in a first state and substantially antiparallel to the magnetic moment of the pinned layer in a second state. The pinned layer has a physical dimension to produce an offset magnetic field corresponding to a first switching current of the MTJ structure to enable switching between the first state and the second state when a first voltage is applied from the bit line to a source line coupled to an access transistor and a second switching current to enable switching between the second state and the first state when the first voltage is applied from the source line to the bit line.

Abstract translation: 存储单元包括磁隧道结（MTJ）结构，其包括耦合到位线和固定层的自由层。 自由层的磁矩基本上平行于处于第一状态的被钉扎层的磁矩，并且在第二状态下基本上与销钉层的磁矩反平行。 固定层具有物理尺寸以产生对应于MTJ结构的第一开关电流的偏移磁场，以便当第一电压从位线施加到耦合到第一状态的源极线时，能够在第一状态和第二状态之间切换 存取晶体管和第二开关电流，以便当第一电压从源极线施加到位线时，能够在第二状态和第一状态之间切换。

公开(公告)号：US20140010006A1

公开(公告)日：2014-01-09

申请号：US14022364

申请日：2013-09-10

Applicant: QUALCOMM Incorporated

Inventor： Hari M. Rao ,  Jung Pill Kim ,  Seung H. Kang ,  Xiaochun Zhu ,  Taehyun Kim ,  Kangho Lee ,  Xia Li ,  Wah Nam Hsu ,  Wuyang Hao ,  Jungwon Suh ,  Nicholas K. Yu ,  Matthew M. Nowak ,  Steven M. Millendorf ,  Asaf Ashkenazi

IPC: G11C11/14

CPC classification number: G11C11/16 ,  G11C11/14 ,  G11C11/1655 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C17/02 ,  G11C17/16 ,  G11C29/027

Abstract: A memory device includes a magnetic tunnel junction (MTJ) bitcell. The MTJ bitcell includes a first MTJ and a second MTJ. The memory device further includes programming circuitry configured to generate a non-reversible state at the bitcell by applying a program signal to a selected one of the first MTJ and the second MTJ of the bitcell. The non-reversible state corresponds to a value of the MTJ bitcell that is determined by comparing a first value read at the first MTJ and a second value read at the second MTJ.

Abstract translation: 存储器件包括磁性隧道结（MTJ）位单元。 MTJ位单元包括第一MTJ和第二MTJ。 存储器件还包括编程电路，其被配置为通过将程序信号施加到位单元的第一MTJ和第二MTJ中的所选择的一个来在位单元处产生不可逆状态。 不可逆状态对应于通过比较在第一MTJ读取的第一值和在第二MTJ读取的第二值确定的MTJ比特单元的值。

公开(公告)号：US09721634B2

公开(公告)日：2017-08-01

申请号：US14860931

申请日：2015-09-22

Applicant: QUALCOMM Incorporated

Inventor： Xiaochun Zhu ,  Yu Lu ,  Chando Park ,  Seung Hyuk Kang

IPC: G11C11/16 ,  H01L27/22

CPC classification number: G11C11/1659 ,  G11C11/02 ,  G11C11/161 ,  H01L27/228

Abstract: Magnetic tunnel junction (MTJ) memory bit cells that decouple source line layout from access transistor node size to facilitate reduced contact resistance are disclosed. In one example, an MTJ memory bit cell is provided that includes a source plate disposed above and in contact with a source contact for a source node of an access transistor. A source line is disposed above and in electrical contact with the source plate to electrically connect the source line to the source node. The source plate allows the source line to be provided in a higher metal level from the source and drain contacts of the access transistor such that the source line is not in physical contact with (i.e., decoupled from) the source contact. This allows pitch between the source line and drain column to be relaxed from the width of the source and drain nodes without having to increase contact resistance.

公开(公告)号：US09548096B1

公开(公告)日：2017-01-17

申请号：US14835871

申请日：2015-08-26

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Yu Lu ,  Xiaochun Zhu

IPC: G11C11/00 ,  G11C11/16

CPC classification number: G11C11/1673 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1675 ,  H01L27/228

Abstract: Reverse complement MTJ bit cells employing shared source lines are disclosed. In one aspect, a 2T2MTJ reverse complement bit cell employing shared source line is provided. Bit cell includes first MTJ and second MTJ. Value of first MTJ is complement of value of second MTJ. First bit line is coupled to top layer of first MTJ, and first electrode of first access transistor is coupled to bottom layer of first MTJ. Second bit line is coupled to bottom layer of second MTJ, and first electrode of second access transistor is coupled to top layer of second MTJ. Word line is coupled to second electrode of first access transistor and second access transistor. Shared source line is coupled to third electrode of first access transistor and second access transistor. Employing shared source line allows the bit cell to be designed with reduced parasitic resistance.

Abstract translation: 公开了采用共享源线的反向补码MTJ比特单元。 在一个方面，提供了采用共享源线的2T2MTJ反向补码位单元。 位单元包括第一MTJ和第二MTJ。 第一MTJ的价值是第二MTJ的价值的补充。 第一位线耦合到第一MTJ的顶层，第一存取晶体管的第一电极耦合到第一MTJ的底层。 第二位线耦合到第二MTJ的底层，第二存取晶体管的第一电极耦合到第二MTJ的顶层。 字线耦合到第一存取晶体管和第二存取晶体管的第二电极。 共享源极线耦合到第一存取晶体管和第二存取晶体管的第三电极。 采用共享源极线允许位单元被设计成具有减小的寄生电阻。